Phase error detection in phase lock loop and delay lock loop devices

Abstract

A device includes a lock detect circuit that is structured and arranged to: convert a reference clock to a reference triangle wave; convert a feedback clock to a feedback triangle wave; determine whether the feedback triangle wave is within a tolerance margin that is defined relative to the reference triangle wave; and generate a determiner output that is a first value when the feedback triangle wave is not within the tolerance margin, and a second value when the feedback triangle wave is within the tolerance margin.

What is claimed is: 
     
       1. A lock detect circuit, comprising:
 a first margin setter connected to a first comparator and a second comparator; 
 a second margin setter connected to the first comparator and the second comparator; 
 an OR gate connected to the first comparator and the second comparator; and 
 a lock signal generation unit connected to the OR gate. 
 
     
     
       2. The lock detect circuit of  claim 1 , wherein:
 a first output of the first margin setter is input to the first comparator; 
 a second output of the first margin setter is input to the second comparator; and 
 an output of the second margin setter is input to the first comparator and the second comparator. 
 
     
     
       3. The lock detect circuit of  claim 2 , wherein an output of the first comparator and an output of the second comparator are input to the OR gate. 
     
     
       4. The lock detect circuit of  claim 3 , wherein an output of the OR gate is input to the lock signal generation unit. 
     
     
       5. The lock detect circuit of  claim 2 , wherein:
 the first output of the first margin setter is a first reference signal that is offset from a voltage of a middle signal by a first amount; and 
 the second output of the first margin setter is a second reference signal that is offset from the voltage of the middle signal by a second amount. 
 
     
     
       6. The lock detect circuit of  claim 5 , wherein the first reference signal and the second reference signal each has a same frequency and a same phase as the middle signal. 
     
     
       7. The lock detect circuit of  claim 1 , further comprising:
 a first ramp generator connected to the first margin setter; and 
 a second ramp generator connected to the second margin setter. 
 
     
     
       8. The lock detect circuit of  claim 1 , wherein the lock signal generation unit comprises an integrator and a third comparator. 
     
     
       9. The lock detect circuit of  claim 8 , wherein an output of the OR gate is input to the integrator. 
     
     
       10. The lock detect circuit of  claim 9 , wherein an output of the integrator is input to the third comparator. 
     
     
       11. The lock detect circuit of  claim 10 , wherein a predefined timeout voltage is input to the third comparator. 
     
     
       12. The lock detect circuit of  claim 11 , wherein the third comparator outputs a lock signal.