Fast transient low drop-out voltage regulator for a voltage-mode driver

Abstract

An example voltage regulator includes an output transistor that includes a source coupled to a first voltage supply node and a drain coupled to an output node. The voltage regulator further includes a first transistor that includes a source coupled to the output node, and a second transistor that includes a source coupled to a gate of the output transistor and a drain coupled to a second voltage supply node. The voltage regulator further includes a resistor coupled between the second voltage supply node and a first node that includes the drain of the first transistor and a gate of the second transistor. The voltage regulator further includes an error amplifier that includes a first input coupled to a reference voltage node, a second input coupled to the output node, and an output coupled to a gate of the first transistor.

What is claimed is: 
     
       1. A voltage regulator, comprising:
 an output transistor that includes a source coupled to a first voltage supply node and a drain coupled to an output node; 
 a first transistor that includes a source coupled to the output node; 
 a second transistor that includes a source coupled to a gate of the output transistor and a drain coupled to a second voltage supply node; 
 a resistor coupled between the second voltage supply node and a first node that includes the drain of the first transistor and a gate of the second transistor; and 
 an error amplifier that includes a first input coupled to a reference voltage node, a second input coupled to the output node, and an output coupled to a gate of the first transistor. 
 
     
     
       2. The voltage regulator of  claim 1 , further comprising:
 a current source coupled between the first voltage supply node and a second node that includes the source of the second transistor and the gate of the output transistor. 
 
     
     
       3. The voltage regulator of  claim 1 , wherein each of the output transistor, the first transistor, and the second transistor is an n-channel field effect transistor (FET). 
     
     
       4. The voltage regulator of  claim 1 , wherein a voltage between the first voltage supply node and the second voltage supply node is an input voltage of the voltage regulator, and wherein a voltage of the output node is an output voltage of the voltage regulator. 
     
     
       5. The voltage regulator of  claim 1 , further comprising:
 a capacitor coupled between the output node and the first voltage supply node. 
 
     
     
       6. The voltage regulator of  claim 1 , wherein the error amplifier includes a folded cascode amplifier. 
     
     
       7. The voltage regulator of  claim 6 , wherein the folded cascode amplifier includes a source-coupled transistor pair, which includes a source node coupled to a current source and drains coupled to an output circuit, wherein the output circuit is disposed between the first voltage supply node and the second voltage supply node, and wherein gates of the source-coupled transistor pair are coupled to the reference voltage node and the output node, respectively. 
     
     
       8. The voltage regulator of  claim 7 , wherein the output circuit includes:
 a first gate-coupled transistor pair that includes sources coupled to the first voltage supply node and drains respectively coupled to the drains of the source-coupled transistor pair; and 
 second, third, and fourth gate-coupled transistor pairs coupled in cascode between the second voltage supply node and the first gate-coupled transistor pair. 
 
     
     
       9. A driver circuit, comprising:
 a voltage-mode output driver; and 
 a voltage regulator coupled to the voltage-mode output driver, the voltage regulator providing an output voltage to the voltage-mode output driver, the voltage regulator including:
 an output transistor that includes a source coupled to a first voltage supply node and a drain coupled to an output node, which supplies the output voltage; 
 a first transistor that includes a source coupled to the output node; 
 a second transistor that includes a source coupled to a gate of the output transistor and a drain coupled to a second voltage supply node; 
 a resistor coupled between the second voltage supply node and a first node that includes the drain of the first transistor and a gate of the second transistor; and 
 an error amplifier that includes a first input coupled to a reference voltage node, a second input coupled to the output node, and an output coupled to a gate of the first transistor. 
 
 
     
     
       10. The driver circuit of  claim 9 , further comprising:
 a current source coupled between the first voltage supply node and a second node that includes the source of the second transistor and the gate of the output transistor. 
 
     
     
       11. The driver circuit of  claim 9 , wherein each of the output transistor, the first transistor, and the second transistor is an n-channel field effect transistor (FET). 
     
     
       12. The driver circuit of  claim 9 , wherein the voltage regulator is configured to sink current from the voltage-mode output driver. 
     
     
       13. The driver circuit of  claim 9 , further comprising:
 a capacitor coupled between the output node and the first voltage supply node. 
 
     
     
       14. The driver circuit of  claim 9 , wherein the error amplifier includes a folded cascode amplifier. 
     
     
       15. The driver circuit of  claim 14 , wherein the folded cascode amplifier includes a source-coupled transistor pair, which includes a source node coupled to a current source and drains coupled to an output circuit, wherein the output circuit is disposed between the first voltage supply node and the second voltage supply node, and wherein gates of the source-coupled transistor pair are coupled to the reference voltage node and the output node, respectively. 
     
     
       16. The driver circuit of  claim 15 , wherein the output circuit includes:
 a first gate-coupled transistor pair that includes sources coupled to the first voltage supply node and drains respectively coupled to the drains of the source-coupled transistor pair; and 
 second, third, and fourth gate-coupled transistor pairs coupled in cascode between the second voltage supply node and the first gate-coupled transistor pair. 
 
     
     
       17. A voltage regulator, comprising:
 an output transistor that includes a source coupled to a first voltage supply node and a drain coupled to an output node that supplies a regulated output voltage; 
 a DC regulation loop that includes a first source follower configured to control the regulated output voltage and an error amplifier configured to control the first source follower; and 
 a fast transient loop that includes a second source follower, a resistor, and the first source follower, the second source follower configured to control the output transistor; 
 wherein a voltage between the resistor and the first source follower controls the second source follower. 
 
     
     
       18. The voltage regulator of  claim 17 , wherein the first source follower comprises a first transistor and the output transistor, and the error amplifier is configure to compare the regulated output voltage with a reference voltage to control the regulated output voltage through the first source follower. 
     
     
       19. The voltage regulator of  claim 18 , wherein a difference between the regulated output voltage and the reference voltage drives a source-coupled transistor pair of the error amplifier, and wherein the source-coupled transistor pair drives a cascode branch circuit to output a voltage for controlling the first source follower. 
     
     
       20. The voltage regulator of  claim 18 , wherein the second source follower comprises a second transistor and a current source, and wherein the resistor is coupled between the second supply node and the first source follower.