Semiconductor device and semiconductor system including the same

Abstract

A semiconductor device includes a boot-up signal generator suitable for generating a boot-up signal based on an external reset signal and a specific mode signal; and an internal circuit suitable for performing a boot-up operation based on the boot-up signal.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a boot-up signal generator suitable for generating a boot-up signal based on at least one of an external reset signal and a specific mode signal for each operation section; and 
 an internal circuit suitable for performing a boot-up operation based on the boot-up signal, and 
 wherein the boot-up signal generator generates the boot-up signal based on the external reset signal during a first operation section, and 
 generates the boot-up signal based on the external reset signal and the specific mode signal during a second operation section, exclusive of the first operation section. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first operation section includes an initial operation section corresponding to a power-up section, and
 the second operation section includes a normal operation section subsequent to the initial operation section. 
 
     
     
       3. The semiconductor device of  claim 1 , wherein the specific mode signal includes a signal corresponding to a soft post package repair (sPPR) mode. 
     
     
       4. The semiconductor device of  claim 3 , wherein the internal circuit includes a one-time programmable (OTP) circuit, and
 the boot-up operation in the sPPR mode includes an operation of reading and latching data for replacing one-time programmable (OTP) data that is programmed in the OTP circuit. 
 
     
     
       5. A semiconductor device, comprising:
 a power-up detector suitable for detecting a power-up section of an external power source voltage to generate a power-up signal; 
 a mode signal generator suitable for generating a specific mode signal based on an external mode related signal; 
 an internal reset signal generator suitable for generating an internal reset signal based on an external reset signal; 
 a boot-up signal generator suitable for generating a boot-up signal based on at least one of the internal reset signal and the specific mode signal; and 
 an internal circuit suitable for performing a boot-up operation based on the boot-up signal, 
 wherein the boot-up signal generator generates the boot-up signal based on the internal reset signal during an initial operation section, and 
 generates the boot-up signal based on the internal reset signal and the specific mode signal during a normal operation section that is subsequent to the initial operation section. 
 
     
     
       6. The semiconductor device of  claim 5 , wherein the boot-up signal generator includes:
 a section control unit suitable for generating a first section signal corresponding to the initial operation section, and generating a second section signal activated in the normal operation section based on the specific mode signal; and 
 a boot-up control unit suitable for activating the boot-up signal based on the first section signal and the internal reset signal during the initial operation section, and activating the boot-up signal based on the internal reset signal, the second section signal, and the specific mode signal, during the normal operation section. 
 
     
     
       7. The semiconductor device of  claim 5 , wherein the boot-up control unit includes:
 a first circuit suitable for generating a boot-up starting signal and a boot-up ending signal that are sequentially activated with a predetermined time gap therebetween based on the first and boot-up signals and the first and second section signals; and 
 a second circuit suitable for generating the boot-up signal that is activated based on the boot-up starting signal and deactivated based on the boot-up ending signal. 
 
     
     
       8. The semiconductor device of  claim 7 , wherein the first circuit includes:
 a first initiating pulse generation block suitable for generating a first initiating pulse signal at a moment when the internal reset signal is deactivated; 
 a second initiating pulse generation block suitable for generating a second initiating pulse signal by delaying the first initiating pulse signal by a predetermined time; 
 a boot-up initiating block suitable for outputting the first initiating pulse signal as the boot-up starting signal based on the first section signal and outputting the second initiating pulse signal as the boot-up starting signal based on the second section signal; and 
 a boot-up ending block suitable for generating the boot-up ending signal at a moment when the boot-up signal is deactivated. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein the boot-up control unit activates the boot-up signal after an internal voltage that is used for the reset operation is stabilized. 
     
     
       10. The semiconductor device of  claim 9 , further comprising:
 an internal voltage generation circuit that is activated ahead of a moment when the boot-up signal is activated based on the power-up signal, the first initiating pulse signal, and the second section signal, and deactivated based on the boot-up ending signal. 
 
     
     
       11. The semiconductor device of  claim 8 , wherein the second circuit includes an SR latch circuit. 
     
     
       12. The semiconductor device of  claim 5 , wherein the mode signal generator includes a mode register set (MRS). 
     
     
       13. The semiconductor device of  claim 5 , wherein the specific mode signal corresponding to an sPPR mode. 
     
     
       14. The semiconductor device of  claim 13 , wherein the internal circuit includes a one-time programmable (OTP) circuit, and
 the boot-up operation in the sPPR mode includes an operation of reading and latching data for replacing OTP data that is programmed in the OTP circuit. 
 
     
     
       15. A semiconductor system, comprising:
 a semiconductor device suitable for performing a boot-up operation based on a reset control signal during an initial operation section corresponding to a power-up section of a power source voltage, and performing the boot-up operation based on a mode related signal during a normal operation section that is subsequent to the initial operation section; and 
 a controller suitable for providing the semiconductor device with the power source voltage, the reset control signal and the mode related signal, 
 wherein the semiconductor device generates a specific information signal corresponding to the boot-up operation, and 
 the controller monitors the specific information signal. 
 
     
     
       16. The semiconductor system of  claim 15 , wherein the mode related signal includes a signal corresponding to an sPPR mode. 
     
     
       17. The semiconductor system of  claim 15 , wherein the semiconductor device comprises:
 a power-up detector suitable for detecting a power-up section of the power source voltage to generate a power-up signal; 
 a mode signal generator suitable for generating a specific mode signal based on the mode related signal; 
 an internal reset signal generator suitable for generating an internal reset signal based on an external reset signal; 
 a boot-up signal generator suitable for generating a boot-up signal based on the internal reset signal and the specific mode signal; 
 an internal circuit suitable for reading predetermined fuse data and latching the read fuse data based on the boot-up signal; and 
 a monitoring circuit suitable for transmitting the fuse data that is latched in the internal circuit as the specific information signal to the controller based on the boot-up signal.