Current sampling circuit and method

Abstract

Disclosed is a current sampling circuit including a proportional current output circuit and a full differential common mode negative feedback circuit, specifically the proportional current output circuit is configured to calculate a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current, and to output the first proportional current and the second proportional current to the full differential common mode negative feedback circuit; and the full differential common mode negative feedback circuit is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current. Further disclosed is a current sampling method.

The invention claimed is: 
     
       1. A current sampling circuit, comprising: a proportional current output circuit and a full differential common mode negative feedback circuit,
 the proportional current output circuit is configured to calculate a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current, and to output the first proportional current and the second proportional current to the full differential common mode negative feedback circuit; and 
 the full differential common mode negative feedback circuit is configured to shunt respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network and a bias current in microamps to obtain a first sampling current and a second sampling current, and to output constantly the first sampling current and the second sampling current; and 
 wherein the power device is implemented by a first Lateral Diffusion N-channel Metal-Oxide-Semiconductor (LDNMOS); 
 the proportional current output circuit comprises a second LDNMOS, a third LDNMOS, a fourth LDNMOS and a fifth LDNMOS; and 
 the full differential common mode negative feedback circuit comprises a first P-channel Metal-Oxide-Semiconductor (PMOS), a second PMOS, a third PMOS, a fourth PMOS, a first resistor, a second resistor, a second reference current source, a third reference current source, a fourth reference current source, and a fifth reference current source; and 
 wherein in the proportional current output circuit, the drain of the second LDNMOS is connected with the drain of the fourth LDNMOS and a power supply, the gate of the second LDNMOS is connected with the gate of the first LDNMOS, the gate of the third LDNMOS and a gate driving voltage, the source of the second LDNMOS is connected respectively with the drain of the third LDNMOS and the drain of the fifth LDNMOS; the source of the third LDNMOS is connected respectively with the source of the first LDNMOS and a first end of the first reference current source; the gate of the fourth LDNMOS is connected with the gate of the fifth LDNMOS, the source of the fourth LDNMOS is connected respectively with the source of the first PMOS and the source of the third PMOS in the full differential common mode negative feedback circuit; the source of the fifth LDNMOS is connected respectively with the source of the second PMOS and the source of the fourth PMOS in the full differential common mode negative feedback circuit; 
 in the full differential common mode negative feedback circuit, the gate of the first PMOS is connected with the gate of the second PMOS, the drain of the first PMOS is connected respectively with a first end of the first resistor, the gate of the fourth PMOS and a first end of the third reference current source; the drain of the second PMOS is connected respectively with a first end of the second resistor, the gate of the third PMOS and a first end of the fourth reference current source; the drain of the third PMOS is connected with a first end of the second reference current source; the drain of the fourth PMOS is connected with the fifth reference current source; a second end of the first resistor is connected respectively with a second end of the second resistor, the gate of the first PMOS and the gate of the second PMOS; second ends of the first reference current source, the second reference current source, the third reference current source, the fourth reference current source and the fifth reference current source are all connected to a ground point; and 
 the drain of the first LDNMOS is connected to the power supply. 
 
     
     
       2. A current sampling method, comprising:
 calculating a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current; and 
 shunting respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current, and outputting constantly the first sampling current and the second sampling current; 
 wherein the shunting respectively the first proportional current and the second proportional current using a full differential common mode negative feedback network with a bias current in microamps to obtain a first sampling current and a second sampling current comprises: 
 obtaining the first sampling current I sense+  and the second sampling current I sense−  from the following formula:
     I   sense+   =I   J1   −I   b    
     I   sense−   =I   J2   −I   b−   
 
 where I J1  is the first proportional current, I J2  is the second proportional current, and I b  is the bias current in microamps provided by the full differential common mode negative feedback network. 
 
     
     
       3. The current sampling method according to  claim 2 , wherein the calculating a current output from a power device according to a preset proportion to obtain a first proportional current and a second proportional current comprises:
 calculating a ratio between the current output from the power device and the preset proportion, and taking an obtained ratio as a current value of a proportional branch; 
 determining the first proportional current and the second proportional current according to the current value of the proportional branch.