Apparatuses, multi-chip modules and capacitive chips

Abstract

Some embodiments include a capacitive chip having a plurality of capacitive units. The individual capacitive units include alternating electrode layers and dielectric layers in a capacitor stack. The capacitor stack extends across an undulating topography. The undulating topography has peaks and valleys with the peaks being elevationally offset relative to the valleys by a distance within a range of from about 30 microns to about 100 microns. The capacitor stack includes at least about 10 total layers. Some embodiments include apparatuses and multi-chip modules having capacitor chips.

I claim: 
     
       1. An apparatus, comprising:
 a power supply; 
 an integrated circuit chip; and 
 a capacitive chip electrically coupled between the power supply and the integrated circuit chip and configured to modify power from the power supply to the integrated circuit chip and/or to provide backup power to the chip in the event of power failure; the capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:
 alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography having elevational offsets of from about 30 microns to about 100 microns; 
 the capacitor stack comprising at least about 10 total layers; and 
 wherein the electrode layers and dielectric layers have thicknesses within a range of from about 5 nanometers to about 20 nanometers. 
 
 
     
     
       2. An apparatus, comprising:
 a power supply; 
 an integrated circuit chip; 
 a capacitive chip electrically coupled between the power supply and the integrated circuit chip and configured to modify power from the power supply to the integrated circuit chip and/or to provide backup power to the chip in the event of power failure; the capacitive chip comprising a plurality of capacitive units, the individual capacitive units comprising:
 alternating electrode layers and dielectric layers in a capacitor stack; the capacitor stack extending across an undulating topography having elevational offsets of from about 30 microns to about 100 microns; and 
 the capacitor stack comprising at least about 10 total layers; and 
 
 the apparatus comprising at least about 1 capacitive unit per square millimeter. 
 
     
     
       3. The apparatus of  claim 2  comprising at least about 4 capacitive units per square millimeter. 
     
     
       4. The apparatus of  claim 2  wherein all of the capacitive units are substantially identical to one another in capacitance. 
     
     
       5. The apparatus of  claim 2  wherein at least one of the capacitive units has a substantially different capacitance than another of the capacitive units. 
     
     
       6. The apparatus of  claim 2  wherein the capacitor stack comprises at least about 30 total layers. 
     
     
       7. The apparatus of  claim 2  wherein the capacitor stack comprises at least about 50 total layers. 
     
     
       8. The apparatus of  claim 1  wherein the capacitive chip has capacitive volume within a range of from about 10 μF/mm 3  to about 400 μF/mm 3 . 
     
     
       9. The apparatus of  claim 2  wherein the capacitive chip has capacitive volume within a range of from about 10 μF/mm 3  to about 400 μF/mm 3 .