US9768091B2ActiveUtilityPatentIndex 64
Method of forming an electronic package and structure
Est. expiryFeb 13, 2032(~5.6 yrs left)· nominal 20-yr term from priority
Inventors:ARIPIN AZHAR
H10W 74/00H10W 70/681H10W 72/0198H10W 72/884H10W 90/756H10W 90/736H10W 70/424H10W 70/421H10W 70/415H10W 70/04H10W 74/111H01L 23/49548H01L 2924/181H01L 2224/32245H01L 2224/73265H01L 2224/97H01L 2224/83Y10T29/49117H01L 2924/00H01L 2924/00012H01L 21/4821H01L 23/3107H01L 2224/48247H01L 24/73H01L 2924/07802H01L 23/49541H01L 23/4951H01L 2224/85H01L 2924/15151H01L 24/97
64
PatentIndex Score
5
Cited by
8
References
7
Claims
Abstract
In one embodiment, an electronic package structure includes multiple rows of I/O pads and is formed without a flag portion. An electronic device may be attached to a pair of adjacent inner rows of I/O pads. The pair of adjacent inner rows of I/O pads is configured to support, at least in part, the electronic device, and to receive connective structures, such as wire bonds. Connective structures may electrically connect the electronic device to the multiple rows of I/O pads, and an encapsulating layer covers portions of the I/O pads, the electronic device and the connective structures.
Claims
exact text as granted — not AI-modifiedI claim:
1. An electronic device structure comprising:
a leadframe having a pair of adjacent inner rows of I/O pads and at least one outer row of I/O pads, wherein the pair of adjacent inner rows of I/O pads are physically isolated from each other and each have an interior facing sidewall surface opposing each other;
an electronic device having first and second opposing major surfaces, wherein the second major surface is attached to at least two opposing I/O pads in the pair of adjacent inner rows of I/O pads;
connective structures coupling the first major surface to at least a portion of I/O pads in the pair of adjacent inner rows of I/O pads and the at least one outer row of I/O pads; and
an encapsulating layer covering at least portions of the leadframe, the electronic device and the connective structures, wherein the encapsulating layer is absent from a portion of the interior facing sidewall surface of each of the adjacent inner rows of I/O pads, wherein:
one I/O pad within the pair of adjacent inner rows of I/O pads is attached to the second major surface with a conductive material, and
a second I/O pad within the pair of adjacent inner rows of I/O pads is attached to the second major surface with a non-conductive material.
2. The structure of claim 1 , wherein the electronic device structure is configured as a quad-flat pack no-lead (QFN) package.
3. The structure of claim 1 , wherein the leadframe has at least two outer rows of I/O pads.
4. The structure of claim 1 , wherein the leadframe is absent a flag portion adjacent a central portion of the electronic device.
5. The structure of claim 1 further comprising a slot between the pair of adjacent inner rows of I/O pads underlying the electronic device.
6. The structure of claim 1 , wherein the second major surface is attached with a non-conductive adhesive.
7. The structure of claim 1 , wherein the connective structures comprise wire bonds.Cited by (0)
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