Electrostatic discharge protection device for high voltage

Abstract

A circuit for protecting against electrostatic discharge events has a semiconductor substrate ( 200 ) of first conductivity embedding a first diode in a well ( 260 ) of opposite second conductivity, the diode's anode ( 111 ) tied to an I/O pin-to-be-protected ( 101 ) at a first voltage, and the first diode's cathode ( 112 ) connected to the first drain ( 123 ) of a first MOS transistor in the substrate. The first MOS transistor's first gate ( 122 ) is biased to a second voltage smaller than the first voltage, thereby reducing the first voltage by the amount of the second voltage. In series with the first MOS transistor is a second MOS transistor with its second drain ( 670 ) merged with the first source of the first MOS transistor, and its second source ( 131 ), together with its second gate ( 132 ), tied to ground potential ( 140 ).

We claim: 
     
       1. A circuit for protecting against electrostatic discharge events, comprising:
 a semiconductor substrate of first conductivity embedding a first diode connected to a cascode including at least a first MOS transistor tied to a second MOS transistor in series; 
 the first diode located in a well of opposite second conductivity, the first diode's anode tied to an I/O pin-to-be-protected at a first voltage, and the first diode's cathode connected to the first drain of the first MOS transistor; 
 the first MOS transistor having its first gate connected to a bias node operable to reduce the first voltage by the amount of a second voltage; and 
 the second MOS transistor having its second drain coupled to the first source of the first MOS transistor, and its second source, together with its second gate, tied to a ground node. 
 
     
     
       2. The circuit of  claim 1  wherein the substrate further has a first resistivity so that the second source is coupled to the first drain by a substrate resistance, and the well further has a second resistivity so that the first diode's anode is tied to the first diode's cathode by a well resistance, and the first diode's anode is coupled to the second source by the sum of the substrate and well resistances. 
     
     
       3. The circuit of  claim 1  further including a third diode having its third cathode tied to the I/O pin and its third anode connected to the ground node, thereby providing protection against negative discharge events, while the circuitry with the first diode provides protection against positive discharge events. 
     
     
       4. The circuit of  claim 1  wherein the first drain of the first MOS transistor has a reverse breakdown voltage greater than the first voltage. 
     
     
       5. The circuit of  claim 4  wherein a parasitic silicon-controlled-rectifier (SCR) formed between the second source and the first anode has a trigger voltage V trig , set by the reverse breakdown of the first drain, inversely proportional to the resistance sum, and a holding voltage V hold  directly proportional to the resistance sum. 
     
     
       6. The circuit of  claim 5  wherein an increase of the sum of substrate and well resistances lowers V trig , and a decrease of the sum lowers V hold . 
     
     
       7. The circuit of  claim 5  wherein, for given substrate and well resistivities, V hold  is directly proportional to the SCR spacing between the second source and the first anode. 
     
     
       8. The circuit of  claim 1  further including a merger of the contact regions of the first source and the second drain, thereby reducing the spacing between second source and first anode and thus, for given substrate resistivity, the substrate resistance and V hold . 
     
     
       9. The circuit of  claim 1  wherein the sum of substrate and well resistances is kept large by increasing the semiconductor resistivity, while concurrently the sum is kept small by reducing the spacing between first anode and second source. 
     
     
       10. The circuit of  claim 1  further including one or more additional biased MOS transistors connected in series. 
     
     
       11. The circuit of  claim 1  wherein close proximity of the contacts of first anode and first cathode minimizes the well resistance between the contacts, allowing the parasitic bipolar transistor between well and substrate to pump electrical carriers into the substrate for turning-on a parasitic silicon-controlled-rectifier constituted between first anode and second source. 
     
     
       12. An electrostatic discharge protection circuit, comprising:
 a semiconductor substrate of first conductivity type; 
 a first diode located in a well of opposite second conductivity, the first diode having an anode tied to an I/O pin; 
 a first MOS transistor having a first drain, first source, and first gate, wherein the first gate is coupled to a bias node; 
 a second MOS transistor having a second drain, second source, and second gate, wherein the second drain is coupled to the first source of the first MOS transistor, and the second source, together with the second gate, are coupled to a ground node; and 
 the first diode having a cathode connected to the first drain of the first MOS transistor, such that the first diode is connected between the I/O pin and the first MOS transistor. 
 
     
     
       13. The circuit of  claim 12 , further comprising a second diode having a second cathode connected to the first drain of the first MOS transistor and a second anode connected to the ground node. 
     
     
       14. The circuit of  claim 13 , further including a third diode having a third cathode connected to the I/O pin and a third anode connected to the ground node.