Buffer memory management method, memory control circuit unit and memory storage device

Abstract

A buffer memory management method, a memory control circuit unit and a memory storage device are provided. The method includes allocating a first zone and a second zone in the buffer memory for temporarily storing a plurality of logical address-physical address mapping tables and performing a restore operation on the first zone. The method also includes receiving a write command, wherein a logical address-physical address table to which a logical address indicated by the write command belongs has been temporarily stored in the first zone. The method further includes copying the logical address-physical address table into the second zone, and updating the logical address-physical address table in the second zone.

What is claimed is: 
     
       1. A buffer memory management method for a buffer memory of a memory storage device having a rewritable non-volatile memory module, the buffer memory management method comprising:
 allocating a first zone and a second zone in the buffer memory, wherein the first zone and the second zone respectively has a plurality of continuous buffer units, and at least a portion of the buffer units in the first zone and the second zone are stored with a plurality of logical address-physical address tables; 
 performing a restore operation on the buffer units in the first zone to restore the logical address-physical address mapping tables stored in the first zone to the rewritable non-volatile memory module; 
 receiving a first write command from a host system, wherein the first write command instructs writing first data into a first logical address and a first logical address-physical address mapping table to which the first logical address belongs is temporarily stored in a first buffer unit among the buffer units in the first zone; 
 writing the first data into the rewritable non-volatile memory module, copying the first logical address-physical address mapping table of the first zone to a second buffer unit among the buffer units in the second zone; and 
 updating the first logical address-physical address mapping table temporarily stored in the second buffer unit in the second zone. 
 
     
     
       2. The buffer memory management method of  claim 1 , wherein the step of updating the first logical address-physical address mapping table temporarily stored in the second buffer unit in the second zone further comprises:
 marking the second buffer unit as a dirty status and setting the second zone as an update area, wherein the update area is configured to temporarily store a plurality of updated logical address-physical address mapping tables. 
 
     
     
       3. The buffer memory management method of  claim 2 , further comprising:
 restoring the logical address-physical address mapping tables in all the buffer units in the second zone to the rewritable non-volatile memory module if all the buffer units in the second zone are marked as the dirty status. 
 
     
     
       4. The buffer memory management method of  claim 2 , further comprising:
 selecting a first one of the buffer units in the second zone as the second buffer unit and setting a first pointer to point the second buffer unit according to a precedence of the buffer units in the second zone; and 
 setting the first pointer to point another buffer unit among the buffer units in the second zone after the first logical address-physical address mapping table is copied to the second buffer unit in the second zone, 
 wherein the another buffer unit is the buffer unit next to the second buffer unit and not marked as the dirty status. 
 
     
     
       5. The buffer memory management method of  claim 2 , further comprising:
 receiving a second write command from the host system, 
 wherein the second write command instructs writing second data into a second logical address, and a second logical address-physical address mapping table to which the second logical address belongs is temporarily stored into a third buffer unit among the buffer units in the second zone; and 
 writing the second data into the rewritable non-volatile memory module and updating the second logical address-physical address mapping table temporarily stored in the third buffer unit in the second zone. 
 
     
     
       6. The buffer memory management method of  claim 2 , further comprising:
 receiving a third write command from the host system, 
 wherein the third write command instructs writing third data into a third logical address, and a third logical address-physical address mapping table to which the third logical address belongs is not yet loaded into a mapping table zone; 
 loading the third logical address-physical address mapping table from the rewritable non-volatile memory module, and the third logical address-physical address mapping table is temporarily stored into a fourth buffer unit among the buffer units in the second zone; and 
 writing the third data into the rewritable non-volatile memory module and updating the third logical address-physical address mapping table temporarily stored in the fourth buffer unit in the second zone. 
 
     
     
       7. A memory control circuit unit for controlling a rewritable non-volatile memory module, the memory control circuit unit comprising:
 a host interface configured to couple to a host system; 
 a memory interface configured to couple to the rewritable non-volatile memory module; 
 a buffer memory coupled to the host interface and the memory interface; and 
 a memory management circuit coupled to the host interface, the memory interface, and the buffer memory, and configured to allocate a first zone and a second zone in the buffer memory, wherein each of the first zone and the second zone has a plurality of continuous buffer units and at least a portion of the buffer units in the first zone and the second zone are stored with a plurality of logical address-physical address tables, 
 wherein the memory management circuit is configured to perform a restore operation on the buffer units in the first zone to restore the logical address-physical address mapping tables stored in the first zone to the rewritable non-volatile memory module, 
 wherein the memory management circuit is further configured to receive a first write command from the host system, the first write command instructs writing first data into a first logical address, and a first logical address-physical address mapping table to which the first logical address belongs is temporarily stored in a first buffer unit among the buffer units in the first zone, 
 wherein the memory management circuit is further configured to write the first data into the rewritable non-volatile memory module and copy the first logical address-physical address mapping table of the first zone to a second buffer unit among the buffer units in the second zone, 
 wherein the memory management circuit is further configured to update the first logical address-physical address mapping table temporarily stored in the second buffer unit in the second zone. 
 
     
     
       8. The memory control circuit unit of  claim 7 , wherein the memory management circuit is further configured to mark the second buffer unit as a dirty status and set the second zone as an update area, wherein the update area is configured to temporarily store a plurality of updated logical address-physical address mapping tables. 
     
     
       9. The memory control circuit unit of  claim 8 , wherein the memory management circuit is further configured to restore the logical address-physical address mapping tables in all the buffer units in the second zone to the rewritable non-volatile memory module if all the buffer units in the second zone are marked as the dirty status. 
     
     
       10. The memory control circuit unit of  claim 8 , wherein the memory management circuit is further configured to select a first one of the buffer units in the second zone as the second buffer unit and set a first pointer to point the second buffer unit according to a precedence of the buffer units in the second zone,
 wherein the memory management circuit is further configured to set the first pointer to point another buffer unit among the buffer units in the second zone after copying the first logical address-physical address mapping table of the first zone to the second buffer unit in the second zone, wherein the another buffer unit is the buffer unit next to the second buffer unit and not marked as the dirty status. 
 
     
     
       11. The memory control circuit unit of  claim 8 , wherein the memory management circuit is further configured to receive a second write command from the host system, the second write command instructs writing second data into a second logical address, and a second logical address-physical address mapping table to which the second logical address belongs is temporarily stored into a third buffer unit among the buffer units in the second zone,
 wherein the memory management circuit is configured to write the second data into the rewritable non-volatile memory module and update the second logical address-physical address mapping table temporarily stored in the third buffer unit in the second zone. 
 
     
     
       12. The memory control circuit unit of  claim 8 , wherein the memory management circuit is further configured to receive a third write command from the host system, the third write command instructs writing third data into a third logical address, and a third logical address-physical address mapping table to which the third logical address belongs is not yet loaded into a mapping table zone,
 wherein the memory management circuit is further configured to load the third logical address-physical address mapping table from the rewritable non-volatile memory module, and the third logical address-physical address mapping table is temporarily stored into a fourth buffer unit among the buffer units in the second zone, and 
 wherein the memory management circuit is configured to write the third data into the rewritable non-volatile memory module and update the third logical address-physical address mapping table temporarily stored in the fourth buffer unit in the second zone. 
 
     
     
       13. A memory storage device, comprising:
 a connection interface unit configured to couple to a host system; 
 a rewritable non-volatile memory module; and 
 a memory control circuit unit coupled to the connection interface unit and the rewritable nonvolatile memory module and comprising a buffer memory and configured to allocate a first zone and a second zone in the buffer memory, wherein each of the first zone and the second zone has a plurality of continuous buffer units and at least a portion of the buffer units in the first zone and the second zone are stored with a plurality of logical address-physical address tables, 
 wherein the memory control circuit unit is configured to perform a restore operation on the buffer units in the first zone to restore the logical address-physical address mapping tables stored in the first zone to the rewritable non-volatile memory module, 
 wherein the memory control circuit unit is further configured to receive a first write command from the host system, the first write command instructs writing first data into a first logical address, and a first logical address-physical address mapping table to which the first logical address belongs is temporarily stored in a first buffer unit among the buffer units in the first zone, 
 wherein the memory control circuit unit is configured to write the first data into the rewritable non-volatile memory module, and copy the first logical address-physical address mapping table of the first zone to a second buffer unit among the buffer units in the second zone, 
 wherein the memory control circuit unit is further configured to update the first logical address-physical address mapping table temporarily stored in the second buffer unit in the second zone. 
 
     
     
       14. The memory storage device of  claim 13 , wherein the memory control circuit unit is configured to mark the second buffer unit as a dirty status and set the second zone as an update area, wherein the update area is configured to temporarily store a plurality of updated logical address-physical address mapping tables. 
     
     
       15. The memory storage device of  claim 14 , wherein the memory control circuit unit is further configured to restore the logical address-physical address mapping tables in all the buffer units in the second zone to the rewritable non-volatile memory module if all the buffer units in the second zone are marked as the dirty status. 
     
     
       16. The memory storage device of  claim 14 , wherein the memory control circuit unit is further configured to select a first one of the buffer units in the second zone as the second buffer unit and set a first pointer to point the second buffer unit according to a precedence of the buffer units in the second zone,
 wherein the memory control circuit unit is further configured to set the first pointer to point another buffer unit among the buffer units in the second zone after copying the first logical address-physical address mapping table of the first zone to the second buffer unit in the second zone, wherein the another buffer unit is the buffer unit next to the second buffer unit and not marked as the dirty status. 
 
     
     
       17. The memory storage device of  claim 14 , wherein the memory control circuit unit is further configured to receive a second write command from the host system, the second write command instructs writing second data into a second logical address, and a second logical address-physical address mapping table to which the second logical address belongs is temporarily stored into a third buffer unit among the buffer units in the second zone,
 wherein the memory control circuit unit is configured to write the second data into the rewritable non-volatile memory module and update the second logical address-physical address mapping table temporarily stored in the third buffer unit in the second zone. 
 
     
     
       18. The memory storage device of  claim 14 , wherein the memory control circuit unit is further configured to receive a third write command from the host system, the third write command instructs writing third data into a third logical address, and a third logical address-physical address mapping table to which the third logical address belongs is not yet loaded into a mapping table zone,
 wherein the memory control circuit unit is further configured to load the third logical address-physical address mapping table from the rewritable non-volatile memory module, and the third logical address-physical address mapping table is temporarily stored into a fourth buffer unit among the buffer units in the second zone, and 
 wherein the memory control circuit unit is further configured to write the third data into the rewritable non-volatile memory module and update the third logical address-physical address mapping table temporarily stored in the fourth buffer unit in the second zone.