Semiconductor memory device and method of manufacturing the same

Abstract

An embodiment includes: a semiconductor substrate, a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate; a peripheral region including a transistor on the substrate; a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor. The plurality of first layers and second layers are stacked alternately in the stacking direction, above the transistor disposed in the peripheral region. A plurality of contacts penetrating the plurality of first layers and second layers are connected to the transistor. Moreover, the first layer mainly contains a different material from the second layer.

What is claimed is: 
     
       1. A semiconductor memory device, comprising:
 a semiconductor substrate; 
 a memory cell array region including a plurality of conductive layers connected to memory cells arranged in a stacking direction on the semiconductor substrate, the plurality of conductive layers having a first stepped structure; 
 a peripheral region including a transistor on the semiconductor substrate; 
 a plurality of first layers and second layers stacked alternately in the stacking direction, above the transistor; and 
 a plurality of first contacts penetrating the plurality of first and second layers and connected to the transistor, 
 wherein a first layer of the plurality of first layers includes a different material than a second layer of the plurality of second layers, and 
 the second layer includes a first portion disposed between the plurality of first contacts and a second portion that includes a different material from that of the first portion and is disposed in a portion other than between the plurality of first contacts. 
 
     
     
       2. The semiconductor memory device according to  claim 1 , wherein
 a material configuring the first portion includes a material having a lower permittivity than a material configuring the second portion. 
 
     
     
       3. The semiconductor memory device according to  claim 1 , wherein
 the first portion is an air-filled gap. 
 
     
     
       4. The semiconductor memory device according to  claim 1 , wherein
 more cavities exist in the first portion than in the second portion and the first layer. 
 
     
     
       5. The semiconductor memory device according to  claim 1 , further comprising
 a support penetrating the plurality of first layers and second layers, 
 wherein a lower end of the support is positioned between a lowermost surface of the plurality of first layers and second layers and a surface of the semiconductor substrate. 
 
     
     
       6. The semiconductor memory device according to  claim 1 , further comprising
 a through hole penetrating the plurality of first layers and second layers, in the peripheral region, 
 wherein a lower end of the through hole is positioned between a lowermost surface of the plurality of first layers and second layers and a surface of the semiconductor substrate. 
 
     
     
       7. The semiconductor memory device according to  claim 1 , wherein
 a second contact connected to the semiconductor substrate is further disposed close to an end of the peripheral region, and 
 the first portion of the second layer is positioned between a first contact of the plurality of first contacts and the second contact. 
 
     
     
       8. The semiconductor memory device according to  claim 1 , wherein
 the plurality of first layers and second layers have a second stepped structure. 
 
     
     
       9. The semiconductor memory device according to  claim 1 , wherein
 the transistor is disposed in a periphery of the memory cell array region.