Class-D amplifier circuits

Abstract

Methods and apparatus for Class-D amplifier circuits with improved power efficiency. The circuit has an output stage with at least first and second switches and a modulator that receives an input signal to be amplified, S IN , and a first clock signal f SW . The modulator controls the duty cycles of the first and second switches, within a switching cycle based on the input signal, wherein the switching cycle has a switching frequency based on the first clock signal. A frequency controller controls the frequency of the first clock signal in response to an indication of the amplitude of the input signal so as to provide a first switching frequency at a first input signal amplitude and a second, lower, switching frequency at a second, lower, input signal amplitude. A lower switching frequency can be tolerated at low signal amplitudes and varying the switching frequency in this way thus maintains stability while reducing switching power losses.

What is claimed is: 
     
       1. A Class-D amplifier circuit for amplifying an input signal comprising:
 an output stage comprising at least first and second switches; 
 a modulator comprising a signal input for receiving said input signal and a clock input for receiving a first clock signal, the modulator being configured to generate a switch control signal to control the duty cycles of said first and second switches within a switching cycle based on said input signal and to output the switch control signal to the output stage, wherein said switching cycle has a switching frequency based on said first clock signal; and 
 a frequency controller configured to receive a version of the switch control signal output from the modulator and to control the frequency of said first clock signal based on said received switch control signal. 
 
     
     
       2. A Class-D amplifier circuit as claimed in  claim 1  wherein the frequency controller is configured to control the frequency of said first clock signal so as to provide a first switching frequency at a first value of duty cycle of said first and second switches and a second switching frequency at a second value of duty cycle of said first and second switches, wherein said second value of duty cycle corresponds to a lower output signal amplitude than said first value of duty cycle and wherein the second switching frequency is lower than the first switching frequency. 
     
     
       3. A Class-D amplifier circuit as claimed in  claim 1  wherein the frequency controller is configured to monitor the switch control signal and control the frequency of said first clock signal based on a determined pulse width or duty cycle of pulses in the switch control signal. 
     
     
       4. A Class-D amplifier circuit as claimed in  claim 3  wherein the comprise a counter configured to produce a count value for each switching cycle corresponding to pulse width or duty cycle of pulses in the switch control signal, the counter being clocked by a second clock signal wherein the second clock signal has a greater frequency than said first clock signal. 
     
     
       5. A Class-D amplifier circuit as claimed in  claim 4  wherein the second clock signal has a frequency which is at least 64 times greater than a maximum frequency of the first clock signal. 
     
     
       6. A Class-D amplifier circuit as claimed in  claim 4  wherein the frequency controller is configured to compare the count value to a count threshold to determine the switching frequency of the first clock signal. 
     
     
       7. A Class-D amplifier circuit as claimed in  claim 6  wherein the count threshold depends on the then present switching frequency of the first clock signal. 
     
     
       8. A Class-D amplifier circuit as claimed in  claim 6  wherein the frequency of the second clock signal varies in accordance with frequency changes to the first clock signal. 
     
     
       9. A Class-D amplifier circuit as claimed in  claim 6  wherein the counter is configured to start counting at the beginning of a control pulse and stop counting at the end of a control pulse such that the count value corresponds to the temporal width of the control pulse. 
     
     
       10. A Class-D amplifier circuit as claimed in  claim 6  wherein the counter is an up-down counter configured to increment for part of the switching cycle and decrement for the rest of the switching cycle based on the duration of the control pulse such that the count value corresponds to a difference in variation of the duty cycle from 50%. 
     
     
       11. A class-D amplifier as claimed in  claim 1  wherein said modulator comprises a reference waveform generator for generating a ramped reference waveform at a frequency based on said first clock signal and a comparator for comparing a first signal derived from the input signal with the ramped reference waveform to generate said switch control signal. 
     
     
       12. A class-D amplifier as claimed in  claim 11  wherein said frequency controller is configured such that any change in switching frequency is substantially synchronised to the top or bottom of the ramp of the reference voltage waveform. 
     
     
       13. A class-D amplifier as claimed in  claim 11  wherein said reference waveform generator is configured such that the amplitude of the reference waveform is substantially the same at said first and second switching frequencies. 
     
     
       14. A class-D amplifier as claimed in  claim 13  wherein said frequency controller is configure to generate a gain control signal indicating any changes in said switching frequency and the reference waveform generator is configured to receive the gain control signal and adjust the slope of the ramp waveform based on said gain control signal to compensate for any change in switching frequency. 
     
     
       15. A class-D amplifier as claimed in  claim 1  wherein said frequency controller is configured to implement the transition from the first switching frequency to the second switching frequency or the second switching frequency to from the first switching frequency over a period of time. 
     
     
       16. A driver circuit comprising a class-D amplifier circuit as claimed in  claim 1  wherein said driver circuit is arranged to drive at least one of: an audio transducer, a haptic transducer, an ultrasound transducer; or an electromechanical actuator or motor. 
     
     
       17. An electronic device comprising a class-D amplifier as claimed in  claim 1  wherein the device is at least one of: a portable device; a battery powered device; a mobile communications device; a computing device; a gaming device; an audio device; or an ultrasonic device. 
     
     
       18. A Class-D amplifier circuit for amplifying an input signal comprising:
 an output stage comprising at least first and second switches; 
 a modulator comprising a signal input for receiving said input signal and a clock input for receiving a first clock signal, the modulator being configured to control the duty cycles of said first and second switches within a switching cycle based on said input signal, wherein said switching cycle has a switching frequency based on said first clock signal; and 
 a frequency controller configured to determine the duty cycle of the first or second switches and to control the frequency of said first clock signal based on the determined duty cycle of the first or second switches. 
 
     
     
       19. A Class-D amplifier circuit for amplifying an audio signal comprising:
 an output stage comprising at least first and second switches; 
 a modulator comprising a signal input for receiving said audio signal and a clock input for receiving a first clock signal, the modulator being configured to generate a PWM control signal to control the duty cycles of said first and second switches based on said audio signal and a cyclic reference waveform and output the PWM control signal to the output stage, wherein the frequency of said cyclic reference waveform depends on said first clock signal; and 
 a frequency controller configured to receive the PWM control signal output from the modulator and to control the frequency of said first clock signal based on the received PWM control signal. 
 
     
     
       20. A Class-D amplifier circuit as claimed in  claim 19  wherein the frequency controller is configured to control the frequency of said first clock signal based on the duty cycle of said PWM control signal.