Forward error correction (FEC) data transmission system

Abstract

A device implementing a forward error correction data transmission system may include at least one processor circuit. The at least one processor circuit may be configured to perform line encoding on a data stream received from a media access control (MAC) module, and periodically insert alignment markers after every number of blocks of the data stream, where the alignment markers are determined based at least in part on a data rate of an associated port. The at least one processor circuit may be further configured to transcode the data stream, where each alignment marker remains contiguous in the transcoded data stream. The at least one processor circuit may be further configured to add parity information to the transcoded data stream. The at least one processor circuit may be further configured to transmit the transcoded data stream over at least one physical lane of the associated port.

What is claimed is: 
     
       1. A device comprising:
 at least one processor circuit configured to:
 perform line encoding on a data stream received from a media access control (MAC) module; 
 periodically insert a plurality of alignment markers after every number of blocks of the data stream; 
 transcode the data stream, wherein each alignment marker of the plurality of alignment markers remains contiguous in the transcoded data stream; 
 add parity information to the transcoded data stream; and 
 transmit the transcoded data stream over no more than two physical lanes of an associated port. 
 
 
     
     
       2. The device of  claim 1 , wherein at the at least one processor circuit is further configured to:
 distribute symbols of the transcoded data stream to the no more than two physical lanes of the associated port; and 
 transmit the distributed symbols over the no more than two physical lanes of the associated port, wherein each alignment marker of the plurality of alignment markers remains contiguous over one of the no more than two physical lanes. 
 
     
     
       3. The device of  claim 2 , wherein the plurality of alignment markers are inserted every 81,916 blocks. 
     
     
       4. The device of  claim 3 , wherein the blocks comprise 66-bit blocks. 
     
     
       5. The device of  claim 3 , wherein the plurality of alignment markers are respectively designated as AM 0 , AM 1 , AM 2 , and AM 3 . 
     
     
       6. The device of  claim 2 , wherein the plurality of alignment markers comprises a first number of alignment markers when a data rate is a first data rate or a second data rate that is different than the first data rate. 
     
     
       7. The device of  claim 6 , wherein the plurality of alignment markers comprises a second number of alignment markers when the data rate is a third data rate that is greater than the first and second data rates. 
     
     
       8. The device of  claim 1 , wherein the line encoding comprises a 64 b/66 b line encoding. 
     
     
       9. The device of  claim 1 , wherein the no more than two physical lanes of the associated port comprises a single physical lane of the associated port. 
     
     
       10. A computer program product comprising instructions stored in a non-transitory computer-readable storage medium, the instructions comprising:
 instructions to periodically insert a plurality of alignment markers after every number of blocks of a line encoded data stream; 
 instructions to transcode the line encoded data stream; 
 instructions to perform forward error correction (FEC) encoding on the transcoded data stream; and 
 instructions to transmit the FEC encoded data stream over no more than two physical lanes of an associated port. 
 
     
     
       11. The computer program product of  claim 10 , wherein the plurality of alignment markers are respectively designated as AM 0 , AM 1 , AM 2 , and AM 3 , and the plurality of alignment markers are inserted after every 81,916 blocks. 
     
     
       12. The computer program product of  claim 10 , wherein each alignment marker of the plurality of alignment markers remains contiguous in the FEC encoded data stream. 
     
     
       13. The computer program product of  claim 10 , the instructions further comprising:
 instructions to distribute symbols of the FEC encoded data stream to the no more than two physical lanes of the associated port; and 
 instructions to transmit the distributed symbols of the FEC encoded data stream over the no more than two physical lanes of the associated port, wherein each alignment marker of the plurality of alignment markers remains contiguous over one of the no more than two physical lanes. 
 
     
     
       14. A method comprising:
 performing line encoding on a data stream received from a media access control (MAC) module; 
 periodically inserting a plurality of alignment markers after every number of blocks of the data stream; 
 transcoding the data stream, wherein each alignment marker of the plurality of alignment markers remains contiguous in the transcoded data stream; 
 adding parity information to the transcoded data stream; 
 distributing symbols of the transcoded data stream to no more than two physical lanes of an associated port; and 
 transmitting the symbols of the transcoded data stream over the no more than two physical lane of the associated port. 
 
     
     
       15. The method of  claim 14 , wherein each alignment marker of the plurality of alignment markers remains contiguous over at least one of the no more than two physical lanes. 
     
     
       16. The method of  claim 15 , wherein the plurality of alignment markers are inserted every 81,916 blocks. 
     
     
       17. The method of  claim 16 , wherein the blocks comprise 66-bit blocks. 
     
     
       18. The method of  claim 16 , wherein the plurality of alignment markers comprise AM 0 , AM 1 , AM 2 , and AM 3 . 
     
     
       19. The method of  claim 15 , wherein the plurality of alignment markers comprises a first number of alignment markers when a data rate is a first data rate or a second data rate that is different than the first data rate. 
     
     
       20. The method of  claim 19 , wherein the plurality of alignment markers comprises a second number of alignment markers when the data rate is a third data rate that is greater than the first and second data rates.