Method of operating memory controller and methods for devices having the same

Abstract

A method of operating a memory controller includes allocating a new entry whenever a write command is input from a host; and transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state.

What is claimed is: 
     
       1. A method of operating a memory controller comprising:
 allocating a new entry whenever a write command is input from a host; and 
 transferring data corresponding to an entry in a specific state among a plurality of states to the host in response to a read command output from the host, 
 wherein the plurality of states are a FREE state, a WRITE state, a WRITE OLD state, a READ state, a PEND state, a PEND OLD state, a CACHE state, and a DEL state, and 
 the specific state is at least one of the PEND state, the PEND OLD state, or the CACHE state. 
 
     
     
       2. The method of operating a memory controller of  claim 1 , wherein the allocating includes:
 allocating a first entry for a first write command including a first logical block address (LBA) and first data; and 
 allocating a second entry for a second write command including a second LBA and second data. 
 
     
     
       3. The method of operating a memory controller of  claim 2 , wherein the first LBA and the second LBA are equal to each other. 
     
     
       4. The method of operating a memory controller of  claim 3 , further comprising:
 mapping between a first buffer address which indicates a first buffer region of a buffer to store the first data and the first LBA; and 
 mapping between a second buffer address which indicates a second buffer region of the buffer to store the second data and the second LBA. 
 
     
     
       5. The method of operating a memory controller of  claim 4 , further comprising:
 changing a first state of the first entry according to whether or not the first data starts to be written in the first buffer region and whether or not the first data is completely written in the first buffer region; and 
 changing a second state of the second entry according to whether or not the second data starts to be written in the second buffer region and whether or not the second data is completely written in the second buffer region, 
 wherein the first state and the second state are different from each other at a specific time. 
 
     
     
       6. The method of operating a memory controller of  claim 5 , wherein the specific time is a time when the first data and the second data is written at the same time. 
     
     
       7. The method of operating a memory controller of  claim 5 , further comprising:
 changing the first state from the WRITE state to the WRITE OLD state and maintaining the second state in the WRITE state when the second data is written in the second buffer region while the first data is written in the first buffer region. 
 
     
     
       8. The method of operating a memory controller of  claim 7 , further comprising:
 changing the first state from the WRITE OLD state to the PEND OLD state and maintaining the second state in the WRITE state when the first data is completely written in the first buffer region while the second data is written in the second buffer region. 
 
     
     
       9. The method of operating a memory controller of  claim 8 , further comprising:
 changing the second state from the WRITE state to the PEND state and, at the same time, changing the first state from the PEND OLD state to the DEL state when the second data is completely written in the second buffer region. 
 
     
     
       10. The method of operating a memory controller of  claim 9 , further comprising:
 informing a process being executed by a CPU in accordance with firmware of a change of the first state from the PEND OLD state to the DEL state. 
 
     
     
       11. The method of operating a memory controller of  claim 1 , wherein the specific state indicates that the data which corresponds to the entry that is in the specific state is data, among a plurality of data stored in a buffer, that was stored in the buffer most recently at a time when the read command is received. 
     
     
       12. The method of operating a memory controller of  claim 1 , wherein a representation of the specific state includes a bit which indicates whether the data is data read by a prefetch operation. 
     
     
       13. The method of operating a memory controller of  claim 1 , wherein, the transferring data to the host includes, when write data corresponding to the write command is completely written in a second buffer region of a buffer while read data read by an external memory according to the read command is written in a first buffer region of the buffer,
 transferring the write data to the host.