System and method for combined path tracing in static timing analysis

Abstract

Aspects relate to a computer implemented method for timing analysis and pessimism removal of an integrated circuit. The computer implemented method includes performing, using a processor, a static timing analysis of the integrated circuit and generating timing data, generating a light weight path signature of a path using the generated timing data, performing common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information, and storing, in a storage medium, the light weight path signature and the corresponding CPPR information. The method also includes generating a timing report using the light weight path signature and the corresponding CPPR information, wherein the timing report includes full path details generated using at least the light weight path signature, and reporting the timing report with full path details and corresponding CPPR information.

What is claimed: 
     
       1. A computer implemented method for timing analysis and pessimism removal of an integrated circuit, the computer implemented method comprising:
 performing, using a processor, a static timing analysis of the integrated circuit and generating timing data; 
 generating, using the processor, a light weight path signature of a path using the generated timing data; 
 performing, using the processor, common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information; 
 storing, in a storage medium, the light weight path signature and the CPPR information; 
 generating, using the processor, a timing report using the light weight path signature and the CPPR information, wherein the timing report includes full path details generated using at least the light weight path signature; and 
 reporting, using the processor, the timing report with full path details and corresponding CPPR information. 
 
     
     
       2. The computer implemented method of  claim 1 , wherein generating, using the processor, the light weight path signature of the path using the generated timing data comprises:
 selecting a path-endpoint node of the path from the timing data; 
 tracing the path backwards from the path-endpoint node; 
 selecting each branch-point node taken at each stage of backward tracing and pruning out unselected nodes; and 
 organizing the path-endpoint node and the selected branch-point nodes into the light weight path signature. 
 
     
     
       3. The computer implemented method of  claim 1 , wherein generating, using the processor, the light weight path signature of the path using the generated timing data comprises:
 selecting a path-start node of the path from the timing data; 
 tracing the path forwards from the path-start node; 
 selecting each branch-point node taken at each stage of forward tracing and pruning out unselected nodes; and 
 organizing the path-start node and the selected branch-point nodes into the light weight path signature. 
 
     
     
       4. The computer implemented method of  claim 1 , further comprising:
 performing, using the processor, a static timing analysis of the integrated circuit and generating timing data for a plurality of paths; 
 generating, using the processor, a plurality of light weight path signatures for each of the plurality of paths using the generated timing data; 
 performing, using the processor, common path pessimism removal (CPPR) using each of the plurality of light weight path signatures and generating a plurality of corresponding CPPR information for each of the plurality of light weight path signatures; 
 storing, in a storage medium, the plurality of light weight path signatures and the plurality of corresponding CPPR information; 
 generating, using the processor, a timing report using the plurality of light weight path signatures and the plurality of corresponding CPPR information, wherein the timing report includes full path details generated for each of the plurality of light weight path signatures; and 
 reporting, using the processor, the timing report with full path details and corresponding CPPR information. 
 
     
     
       5. The computer implemented method of  claim 1 , wherein the static timing analysis is performed using a plurality of corner-based timing runs. 
     
     
       6. The computer implemented method of  claim 5 , wherein the static timing analysis is a statistical static timing analysis (SSTA). 
     
     
       7. The computer implemented method of  claim 1 , wherein performing, using the processor, common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information comprises:
 building the full path details using the light weight path signature and structure mapping information of the integrated circuit; 
 identifying a common path portion from the full path details; 
 calculating credit information for the identified common path portion; and 
 including the credit information in the CPPR information. 
 
     
     
       8. The computer implemented method of  claim 1 , wherein generating, using the processor, the timing report using the light weight path signature and the corresponding CPPR information comprises:
 selecting the light weight path signature and the corresponding CPPR information; 
 generating the full path details using the light weight path signature and structure mapping information of the integrated circuit; 
 applying the CPPR information to the full path details; and 
 generating the timing report that includes the full path details. 
 
     
     
       9. The computer implemented method of  claim 1 , wherein storing, in the storage medium, the light weight path signature and the corresponding CPPR information comprises:
 caching the light weight path signature and corresponding CPPR information, wherein the storage medium is at least one from a group consisting of a central processing unit (CPU) cache, a graphics processing unit (GPU) cache, a disk cache, a page cache, a web cache, a buffer, and a distributed cache. 
 
     
     
       10. A system for timing analysis and pessimism removal, the system comprising:
 an integrated circuit comprising one or more paths; 
 a storage medium having computer readable instructions; and 
 a processor configured to execute the computer readable instructions, the computer readable instructions comprising:
 performing, using a processor, a static timing analysis of the integrated circuit and generating timing data; 
 generating, using the processor, a light weight path signature of a path using the generated timing data; 
 performing, using the processor, common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information; 
 storing, in a storage medium, the light weight path signature and the CPPR information; 
 generating, using the processor, a timing report using the light weight path signature and the CPPR information, wherein the timing report includes full path details generated using at least the light weight path signature; and 
 reporting, using the processor, the timing report with full path details and corresponding CPPR information. 
 
 
     
     
       11. The system of  claim 10 , wherein generating, using the processor, the light weight path signature of the path using the generated timing data comprises:
 selecting a path-endpoint node of the path from the timing data; 
 tracing the path backwards from the path-endpoint node; 
 selecting each branch-point node taken at each stage of backward tracing and pruning out unselected nodes; and 
 organizing the path-endpoint node and the selected branch-point nodes into the light weight path signature. 
 
     
     
       12. The system of  claim 10 , wherein generating, using the processor, the light weight path signature of the path using the generated timing data comprises:
 selecting a path-start node of the path from the timing data; 
 tracing the path forwards from the path-start node; 
 selecting each branch-point node taken at each stage of forward tracing and pruning out unselected nodes; and 
 organizing the path-start node and the selected branch-point nodes into the light weight path signature. 
 
     
     
       13. The system of  claim 10 , wherein the computer readable instructions that are configured to execute on the processor further comprise:
 performing, using the processor, a static timing analysis of the integrated circuit and generating timing data for a plurality of paths; 
 generating, using the processor, a plurality of light weight path signatures for each of the plurality of paths using the generated timing data; 
 performing, using the processor, common path pessimism removal (CPPR) using each of the plurality of light weight path signatures and generating a plurality of corresponding CPPR information for each of the plurality of light weight path signatures; 
 storing, in a storage medium, the plurality of light weight path signatures and the plurality of corresponding CPPR information; 
 generating, using the processor, a timing report using the plurality of light weight path signatures and the plurality of corresponding CPPR information, wherein the timing report includes full path details generated for each of the plurality of light weight path signatures; and 
 reporting, using the processor, the timing report with full path details and corresponding CPPR information. 
 
     
     
       14. The system of  claim 10 , wherein performing, using the processor, common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information comprises:
 building the full path details using the light weight path signature and structure mapping information of the integrated circuit; 
 identifying a common path portion from the full path details; 
 calculating credit information for the identified common path portion; and 
 including the credit information in the CPPR information. 
 
     
     
       15. The system of  claim 10 , wherein generating, using the processor, the timing report using the light weight path signature and the corresponding CPPR information comprises:
 selecting the light weight path signature and the corresponding CPPR information; 
 generating the full path details using the light weight path signature and structure mapping information of the integrated circuit; 
 applying the CPPR information to the full path details; and 
 generating the timing report that includes the full path details. 
 
     
     
       16. The system of  claim 10 , wherein storing, in the storage medium, the light weight path signature and the corresponding CPPR information comprises:
 caching the light weight path signature and corresponding CPPR information, wherein the storage medium is at least one from a group consisting of a central processing unit (CPU) cache, a graphics processing unit (GPU) cache, a disk cache, a page cache, a web cache, a buffer, and a distributed cache. 
 
     
     
       17. A computer program product for timing analysis and pessimism removal of an integrated circuit, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, the program instructions executable by a processor to cause the processor to:
 perform a static timing analysis of the integrated circuit and generating timing data; 
 generate a light weight path signature of a path using the generated timing data; 
 perform common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information; 
 store, in the computer readable storage medium, the light weight path signature and the CPPR information; 
 generate a timing report using the light weight path signature and the CPPR information, wherein the timing report includes full path details generated using at least the light weight path signature; and 
 report the timing report with full path details and corresponding CPPR information. 
 
     
     
       18. The computer program product of  claim 17 , wherein generating the light weight path signature of the path using the generated timing data comprises:
 selecting a path-endpoint node of the path from the timing data; 
 tracing the path backwards from the path-endpoint node; 
 selecting each branch-point node taken at each stage of backward tracing and pruning out unselected nodes; and 
 organizing the path-endpoint node and the selected branch-point nodes into the light weight path signature. 
 
     
     
       19. The computer program product of  claim 17 , wherein the program instructions executable by the processor to cause the processor to further:
 perform static timing analysis of the integrated circuit and generating timing data for a plurality of paths; 
 generate a plurality of light weight path signatures for each of the plurality of paths using the generated timing data; 
 perform common path pessimism removal (CPPR) using each of the plurality of light weight path signatures and generating a plurality of corresponding CPPR information for each of the plurality of light weight path signatures; 
 store, in the computer readable storage medium, the plurality of light weight path signatures and the plurality of corresponding CPPR information; 
 generate a timing report using the plurality of light weight path signatures and the plurality of corresponding CPPR information, wherein the timing report includes full path details generated for each of the plurality of light weight path signatures; and 
 report the timing report with full path details and corresponding CPPR information. 
 
     
     
       20. The computer program product of  claim 17 ,
 wherein performing common path pessimism removal (CPPR) using the light weight path signature and generating CPPR information comprises:
 building the full path details using the light weight path signature and structure mapping information of the integrated circuit; 
 identifying a common path portion from the full path details; 
 calculating credit information for the identified common path portion; and 
 including the credit information in the CPPR information, and 
 
 wherein generating the timing report using the light weight path signature and the corresponding CPPR information comprises
 selecting the light weight path signature and the corresponding CPPR information; 
 generating the full path details using the light weight path signature and structure mapping information of the integrated circuit; 
 applying the CPPR information to the full path details; and 
 generating the timing report that includes the full path details.