Memory mirroring utilizing single write operations

Abstract

Memory system enabling memory mirroring in single write operations for the primary and backup data storage. The memory system utilizes a memory channel including one or more latency groups, with each latency group encompassing a number of memory modules that have the same signal timing to the controller. A primary copy and a backup copy of a data element can be written to two memory modules in the same latency group of the channel and in a single write operation. The buses of the channel may have the same trace length to each of the memory modules within a latency group.

What is claimed is: 
     
       1. A system comprising:
 a memory controller configured to transmit memory data to dual-inline memory modules (DIMMs) using two or more communication channels; 
 a first communication channel coupled to said memory controller, the first communication channel comprising a first bus; 
 a first set of DIMMs coupled to said first bus; 
 a second communication channel coupled to said memory controller, wherein the second communication channel comprises second and third buses; 
 a second set of DIMMs coupled to said second bus; and 
 a third set of DIMMs coupled to said third bus, 
 wherein said memory controller is configured to enable storage of a primary copy of data within said second set of DIMMs coupled to said second bus and a secondary copy of data within said third set of DIMMs coupled to said third bus by transmitting a single copy of the data over the second communication channel that is delivered to the second set of DIMMs over the second bus and to the third set of DIMMs over the third bus in a single write operation. 
 
     
     
       2. The system of  claim 1 , wherein the first communication channel coupled to said memory controller comprises the first bus and a fourth bus, and further comprising a fourth set of DIMMs coupled to said fourth bus. 
     
     
       3. The system of  claim 1 , wherein the second communication channel comprises a transmission split comprising the second and third buses, wherein the transmission split comprises splitting a trace line coupled to the memory controller. 
     
     
       4. The system of  claim 3 , wherein the transmission split is disposed within a device package housing the second and third buses and the second and third sets of DIMMs. 
     
     
       5. The system of  claim 1 , wherein said primary copy of data is stored in a first DIMM encompassed in said second set of DIMMs, wherein said secondary copy of data is stored in a second DIMM encompassed in said third set of DIMMs, wherein said first DIMM and said second DIMM are in a first latency group. 
     
     
       6. The system of  claim 5 , wherein said first latency group comprises an even number of DIMMs. 
     
     
       7. The system of  claim 5 , wherein said second bus and said third bus have an approximately same trace length to every DIMM in said first latency group. 
     
     
       8. A memory system comprising:
 a memory controller; 
 a communication channel coupled to said memory controller and comprising a first bus and a second bus, wherein the memory controller is configured to send a data element in a single data signal over the communication channel; and 
 a plurality of memory devices coupled to said communication channel and divided into one or more latency groups, wherein each latency group comprises a respective number of memory devices, wherein said communication channel is configured to deliver the single data signal sent from said memory controller to a first memory device of said respective number of memory devices in a first of the one or more latency groups over the first bus and a second memory device of said respective number of memory devices in the first of the one or more latency groups over the second bus in a single write operation to enable storage of a primary copy of the data element within the first memory device and a secondary copy of the data element within the second memory device. 
 
     
     
       9. The memory system of  claim 8 , wherein each of said plurality of memory devices comprises a dual in-line memory module (DIMM). 
     
     
       10. The memory system of  claim 8 , wherein each latency group comprises a respective even number of memory devices. 
     
     
       11. The memory system of  claim 8 , wherein said one or more latency groups comprise a first latency group, wherein said first latency group comprises the first memory device coupled to the first bus and the second memory device coupled to the second bus. 
     
     
       12. The memory system of  claim 11 , wherein said data element is written into both said first memory device and said second memory device in a single write operation performed by said memory controller. 
     
     
       13. The memory system of  claim 8 , wherein said memory controller comprises a field programmable gate array (FPGA) device. 
     
     
       14. The memory system of  claim 11 , wherein said first bus and said second bus have a substantially same trace length. 
     
     
       15. The memory system of  claim 8 , wherein said one or more latency groups further comprise a second latency group, and wherein further each memory device in said second latency group is coupled to a bus that has a different trace length than said first bus. 
     
     
       16. A method of storing data to memory devices, said method comprising:
 sending, with a memory controller, a single write operation to a first memory device and a second memory device via a communication channel; 
 concurrently activating respective chip selects for said first memory device and said second memory device responsive to said single write operation; and 
 concurrently sending, with said memory controller, a data element to said first memory device via a first bus of said communication channel and said second memory device via a second bus of said communication channel while the respective chip selects are concurrently activated to store a primary copy of said data element in said first memory device and to store a backup copy of said data element in said second memory device. 
 
     
     
       17. The method of  claim 16 , wherein said communication channel has substantially a same trace length to said first memory device and said second memory device. 
     
     
       18. The method of  claim 16 , wherein said communication channel comprises shared command/address buses, and wherein said write operation is sent to said first memory device and said second memory device via shared command/address buses of said communication channel. 
     
     
       19. The method of  claim 16  further comprising storing said data element to other memory devices coupled to said communication channel responsive to said single write operation, wherein said communication channel has a same trace length to said first memory device and each of said other memory device. 
     
     
       20. The method of  claim 16 , wherein said first memory device and said second memory device comprise dual in-line memory modules (DIMM) disposed symmetrically with reference to said memory controller. 
     
     
       21. A system comprising:
 a memory controller configured to transmit memory data to dual-inline memory modules (DIMMs) using two or more communication channels; 
 a first communication channel coupled to said memory controller, the first communication channel comprising a first bus; 
 a first set of DIMMs coupled to said first bus; 
 a second communication channel coupled to said memory controller, wherein the second communication channel comprises second and third buses; 
 a second set of DIMMs coupled to said second bus; and 
 a third set of DIMMs coupled to said third bus, 
 wherein said memory controller is configured to enable storage of a primary copy of data within said second set of DIMMs coupled to said second bus and a secondary copy of data within said third set of DIMMs coupled to said third bus by transmitting a single copy of the data over the second communication channel that is delivered to the second set of DIMMs over the second bus with a trace length and to the third set of DIMMs over the third bus with a matched trace length to the second bus.