Non-volatile memory cell and method of operating the same

Abstract

A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region. The select gate is formed above the first diffusion region and the second diffusion region in a polysilicon layer. The floating gate is formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer. The assistant control gate is formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate.

What is claimed is: 
     
       1. A non-volatile memory cell, comprising
 a substrate including a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; 
 a select gate formed above the first diffusion region and the second diffusion region in a polysilicon layer; 
 a floating gate formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer; and 
 an assistant control gate formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate. 
 
     
     
       2. The non-volatile memory cell in  claim 1 , wherein an overlapping region of the floating gate and the fourth diffusion region forms an erase gate region which provides a coupling node at the floating gate. 
     
     
       3. The non-volatile memory cell in  claim 1 , wherein the metal layer is an M1 metal layer provided in a complementary metal-oxide-semiconductor (CMOS) manufacturing process. 
     
     
       4. The non-volatile memory cell in  claim 1 , wherein the metal layer is an M2 metal layer or any conductive routing metal provided in a CMOS manufacturing process. 
     
     
       5. The non-volatile memory cell in  claim 1 , wherein the floating gate and the select gate are formed in a polysilicon layer provided in a CMOS manufacturing process. 
     
     
       6. The non-volatile memory cell in  claim 1 , wherein:
 the first diffusion region, the second diffusion region, and the third diffusion region have a first doping type; and 
 the fourth diffusion region has a second doping type which is complementary to the first doping type. 
 
     
     
       7. The non-volatile memory cell in  claim 1 , wherein:
 the first diffusion region is coupled to a source line; 
 the third diffusion region is coupled to a bit line; 
 the select gate is coupled to a word line; and 
 the assistant control gate is coupled to the source line. 
 
     
     
       8. The non-volatile memory cell in  claim 1 , wherein:
 the first diffusion region is coupled to a source line; 
 the third diffusion region is coupled to a bit line; 
 the select gate is coupled to a word line; and 
 the assistant control gate is coupled to one of the bit line, the word line, and an N-type well of the substrate. 
 
     
     
       9. The non-volatile memory cell in  claim 1 , wherein:
 the first diffusion region is coupled to a source line; 
 the third diffusion region is coupled to a bit line; 
 the select gate is coupled to a word line; and 
 the assistant control gate is coupled to a signal line whose level is equal to a bias level of the bit line, the word line, the source line or an N-type well of the substrate in a same mode of operation. 
 
     
     
       10. A method of operating a non-volatile memory cell which includes:
 a substrate including a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region; 
 a select gate formed above the first diffusion region and the second diffusion region in a polysilicon layer; 
 a floating gate formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer; and 
 an assistant control gate formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate; 
 the method comprising:
 applying a first voltage to the fourth diffusion region and applying a second voltage to the assistant control gate so as to bring electrons onto the floating gate during a program mode of operation; 
 applying a third voltage to the fourth diffusion region and applying a fourth voltage to the assistant control gate as to drag electrons out of the floating gate during an erase mode of operation; 
 wherein: 
 the first voltage and the second voltage are between 0 and a first positive value; 
 the third voltage is between 0 and a second positive value; and 
 the fourth voltage is between 0 and a first negative value. 
 
 
     
     
       11. The method of  claim 10 , further comprising:
 applying a fifth voltage to the first diffusion region, applying a sixth voltage to the third diffusion region and applying a seventh voltage to the select gate during the program mode of operation; 
 wherein:
 the fifth voltage is equal to the first positive value; 
 the sixth voltage is equal to 0; and 
 the seventh voltage is between 0 and a third positive value which is smaller than the first positive value. 
 
 
     
     
       12. The method of  claim 10 , further comprising:
 applying an eighth voltage to the first diffusion region, the select gate, and the third diffusion region during the erase mode of operation, wherein the eighth voltage is equal to 0. 
 
     
     
       13. The method of  claim 10 , further comprising:
 applying an eighth voltage to the first diffusion region, and the third diffusion region and applying an ninth voltage to the select gate during the erase mode of operation; 
 wherein the eight voltage is equal to a second negative value while the ninth voltage is between 0 and the first negative value. 
 
     
     
       14. The method of  claim 10 , wherein the second voltage is larger than the first voltage.