Image sensor configuration

Abstract

An image sensor has an array of light-sensitive pixels. Each pixel of the array includes a photodiode and a plurality of capacitors configured to store charge from the photodiode. The image sensor has an address decoder, coupled to the array of light-sensitive pixels. In at least one mode of operation, portions of the array of light-sensitive pixels to capture respective image exposures. The portions may include interlaced rows of pixels of the array of light-sensitive pixels, blocks of rows of pixels of the array of light-sensitive pixels, interlaced columns of pixels of the array of light-sensitive pixels, interlaced columns and rows of pixels of the array of light-sensitive pixels, blocks of columns and rows of pixels of the array of light-sensitive pixels, etc.

The invention claimed is: 
     
       1. A device, comprising:
 an array of light-sensitive pixels, each pixel of the array including:
 a photodiode; and 
 a plurality of capacitors configured to store charge from the photodiode; and 
 
 an address decoder, coupled to the array of light-sensitive pixels, and which, in at least one mode of operation, controls a plurality of portions of the array of light-sensitive pixels to capture respective image exposures, wherein the address decoder comprises a plurality of row decoders, each row decoder associated with a respective row of the array of light-sensitive pixels and including:
 a memory configured to store row-decoder enablement information; 
 enablement circuitry configured to receive a type signal and to generate an enable signal based on the type signal and the stored row-decoder enablement information; and 
 address circuitry configured to receive a row-address signal and the enable signal, and to selectively enable the respective row of the array of light sensitive pixels based on the row-address signal and the enable signal. 
 
 
     
     
       2. The device of  claim 1  wherein the at least one mode of operation comprises at least one of:
 a mode of operation wherein the plurality of portions comprise interlaced rows of pixels of the array of light-sensitive pixels; and 
 a mode of operation wherein the plurality of portions comprise blocks of rows of pixels of the array of light-sensitive pixels. 
 
     
     
       3. The device of  claim 1  wherein the plurality of capacitors comprises one or more of:
 a first capacitor configured to store a photodiode charge for a first exposure and a second capacitor configured to store a reset noise charge associated with the first exposure; 
 a first capacitor configured to store a photodiode charge for a first exposure and a second capacitor configured to store a photodiode charge for a second exposure; 
 a first capacitor configured to store a photodiode charge for a first exposure, a second capacitor configured to store a reset noise charge associated with the first exposure, a third capacitor configured to store a photodiode charge for a second exposure and a fourth capacitor configured to store a reset noise charge associated with the second exposure; and 
 a first capacitor configured to store a photodiode charge for a first exposure, a second capacitor configured to store a photodiode charge for a second exposure, a third capacitor configured to store a photodiode charge for a third exposure and a fourth capacitor configured to store a photodiode charge for a fourth exposure. 
 
     
     
       4. The device of  claim 1  wherein the array of light-sensitive pixels comprises at least one of:
 a global shutter pixel array; and 
 a rolling blade pixel. 
 
     
     
       5. A device, comprising:
 an array of light-sensitive pixels, each pixel of the array including:
 a photodiode; and 
 a plurality of capacitors configured to store charge from the photodiode; and 
 
 an address decoder, coupled to the array of light-sensitive pixels, and which, in at least one mode of operation, controls a plurality of portions of the array of light-sensitive pixels to capture respective image exposures, wherein the address decoder comprises a plurality of row decoders, and wherein neighboring pixels within each row of the array of light-sensitive pixels are controlled by separate row decoders, each row decoder including:
 a memory configured to store row-decoder enablement information; 
 enablement circuitry configured to receive a type signal and to generate an enable signal based on the type signal and the stored row-decoder enablement information; and 
 address circuitry configured to receive a row-address signal and the enable signal, and to selectively enable pixels of the array of light sensitive pixels controlled by the row decoder based on the row-address signal and the enable signal. 
 
 
     
     
       6. The device of  claim 5  wherein the at least one mode of operation comprises at least one of:
 a mode of operation wherein the plurality of portions comprise interlaced columns of pixels of the array of light-sensitive pixels; 
 a mode of operation wherein the plurality of portions comprise interlaced columns and rows of pixels of the array of light-sensitive pixels; and 
 a mode of operation wherein the plurality of portions comprise blocks of columns and rows of pixels of the array of light-sensitive pixels. 
 
     
     
       7. The device of  claim 5  wherein the plurality of capacitors comprises one or more of:
 a first capacitor configured to store a photodiode charge for a first exposure and a second capacitor configured to store a reset noise charge associated with the first exposure; 
 a first capacitor configured to store a photodiode charge for a first exposure and a second capacitor configured to store a photodiode charge for a second exposure; 
 a first capacitor configured to store a photodiode charge for a first exposure, a second capacitor configured to store a reset noise charge associated with the first exposure, a third capacitor configured to store a photodiode charge for a second exposure and a fourth capacitor configured to store a reset noise charge associated with the second exposure; and 
 a first capacitor configured to store a photodiode charge for a first exposure, a second capacitor configured to store a photodiode charge for a second exposure, a third capacitor configured to store a photodiode charge for a third exposure and a fourth capacitor configured to store a photodiode charge for a fourth exposure. 
 
     
     
       8. The device of  claim 5  wherein the array of light-sensitive pixels comprises at least one of:
 a global shutter pixel array; and 
 a rolling blade pixel. 
 
     
     
       9. A system, comprising:
 an array of light-sensitive pixels, each pixel of the array including:
 a photodiode; and 
 a plurality of capacitors configured to store charge from the photodiode; 
 
 a plurality of illumination sources; and 
 control circuitry, coupled to the array of light-sensitive pixels and the plurality of illumination sources, and which, in at least one mode of operation, controls a plurality of portions of the array of light-sensitive pixels and the plurality of illumination sources to capture respective image exposures, wherein the control circuitry comprises a plurality of row decoders, each row decoder associated with a respective row of the array of light-sensitive pixels and including:
 a memory configured to store row-decoder enablement information; 
 enablement circuitry configured to receive a type signal and to generate an enable signal based on the type signal and the stored row-decoder enablement information; and 
 address circuitry configured to receive a row-address signal and the enable signal, and to selectively enable the respective row of the array of light sensitive pixels based on the row-address signal and the enable signal. 
 
 
     
     
       10. The system of  claim 9  wherein each illumination source of the plurality of illumination sources is associated with a separate wavelength range. 
     
     
       11. The system of  claim 9  wherein the at least one mode of operation comprises at least one of:
 a mode of operation wherein the plurality of portions comprise interlaced rows of pixels of the array of light-sensitive pixels; and 
 a mode of operation wherein the plurality of portions comprise blocks of rows of pixels of the array of light-sensitive pixels. 
 
     
     
       12. The system of  claim 9  wherein the plurality of capacitors comprises one or more of:
 a first capacitor configured to store a photodiode charge for a first exposure and a second capacitor configured to store a reset noise charge associated with the first exposure; 
 a first capacitor configured to store a photodiode charge for a first exposure and a second capacitor configured to store a photodiode charge for a second exposure; 
 a first capacitor configured to store a photodiode charge for a first exposure, a second capacitor configured to store a reset noise charge associated with the first exposure, a third capacitor configured to store a photodiode charge for a second exposure and a fourth capacitor configured to store a reset noise charge associated with the second exposure; and 
 a first capacitor configured to store a photodiode charge for a first exposure, a second capacitor configured to store a photodiode charge for a second exposure, a third capacitor configured to store a photodiode charge for a third exposure and a fourth capacitor configured to store a photodiode charge for a fourth exposure. 
 
     
     
       13. A system, comprising:
 an array of light-sensitive pixels, each pixel of the array including:
 a photodiode; and 
 a plurality of capacitors configured to store charge from the photodiode; 
 
 a plurality of illumination sources; and 
 control circuitry, coupled to the array of light-sensitive pixels and the plurality of illumination sources, and which, in at least one mode of operation, controls a plurality of portions of the array of light-sensitive pixels and the plurality of illumination sources to capture respective image exposures, wherein the control circuitry comprises a plurality of row decoders, and wherein neighboring pixels within each row of the array of light-sensitive pixels are controlled by separate row decoders, each row decoder including:
 a memory configured to store row-decoder enablement information; 
 enablement circuitry configured to receive a type signal and to generate an enable signal based on the type signal and the stored row-decoder enablement information; and 
 address circuitry configured to receive a row-address signal and the enable signal, and to selectively enable pixels of the array of light sensitive pixels controlled by the row decoder based on the row-address signal and the enable signal. 
 
 
     
     
       14. The system of  claim 13  wherein the at least one mode of operation comprises at least one of:
 a mode of operation wherein the plurality of portions comprise interlaced columns of pixels of the array of light-sensitive pixels; 
 a mode of operation wherein the plurality of portions comprise interlaced columns and rows of pixels of the array of light-sensitive pixels; and 
 a mode of operation wherein the plurality of portions comprise blocks of columns and rows of pixels of the array of light-sensitive pixels. 
 
     
     
       15. The system of  claim 13  wherein the plurality of capacitors comprises one or more of:
 a first capacitor configured to store a photodiode charge for a first exposure and a second capacitor configured to store a reset noise charge associated with the first exposure; 
 a first capacitor configured to store a photodiode charge for a first exposure and a second capacitor configured to store a photodiode charge for a second exposure; 
 a first capacitor configured to store a photodiode charge for a first exposure, a second capacitor configured to store a reset noise charge associated with the first exposure, a third capacitor configured to store a photodiode charge for a second exposure and a fourth capacitor configured to store a reset noise charge associated with the second exposure; and 
 a first capacitor configured to store a photodiode charge for a first exposure, a second capacitor configured to store a photodiode charge for a second exposure, a third capacitor configured to store a photodiode charge for a third exposure and a fourth capacitor configured to store a photodiode charge for a fourth exposure. 
 
     
     
       16. A method, comprising:
 controlling, using an address decoder, a plurality of portions of an array of light-sensitive pixels to respectively capture a plurality of image exposures, each pixel of the array including:
 a photodiode; and 
 a plurality of capacitors configured to store charge from the photodiode; and 
 
 storing the captured plurality of image exposures, wherein the address decoder comprises a plurality of row decoders, each row decoder associated with a respective row of the array of light-sensitive pixels and including:
 a memory configured to store row-decoder enablement information; 
 enablement circuitry configured to receive a type signal and to generate an enable signal based on the type signal and the stored row-decoder enablement information; and 
 address circuitry configured to receive a row-address signal and the enable signal, and to selectively enable the respective row of the array of light sensitive pixels based on the row-address signal and the enable signal. 
 
 
     
     
       17. The method of  claim 16  wherein the plurality of portions comprise at least one of:
 interlaced rows of pixels of the array of light-sensitive pixels; and 
 blocks of rows of pixels of the array of light-sensitive pixels. 
 
     
     
       18. The method of  claim 16  wherein the plurality of portions comprise at least one of:
 interlaced columns of pixels of the array of light-sensitive pixels; 
 interlaced columns and rows of pixels of the array of light-sensitive pixels; and 
 blocks of columns and rows of pixels of the array of light-sensitive pixels. 
 
     
     
       19. The method of  claim 16 , comprising at least one of:
 storing a photodiode charge for a first exposure to a first capacitor of a pixel and storing a reset noise charge associated with the first exposure to a second capacitor of the pixel; and 
 storing the photodiode charge for the first exposure to the first capacitor of the pixel and storing a photodiode charge for a second exposure to a second capacitor of the pixel. 
 
     
     
       20. The method of  claim 16 , comprising:
 controlling a plurality of illumination sources during the capturing of the plurality of image exposures. 
 
     
     
       21. A method, comprising:
 controlling, using an address decoder, a plurality of portions of an array of light-sensitive pixels to respectively capture a plurality of image exposures, each pixel of the array including:
 a photodiode; and 
 a plurality of capacitors configured to store charge from the photodiode; and 
 
 storing the captured plurality of image exposures, wherein the address decoder comprises a plurality of row decoders, and wherein neighboring pixels within each row of the array of light-sensitive pixels are controlled by separate row decoders, each row decoder including:
 a memory configured to store row-decoder enablement information; 
 enablement circuitry configured to receive a type signal and to generate an enable signal based on the type signal and the stored row-decoder enablement information; and 
 address circuitry configured to receive a row-address signal and the enable signal, and to selectively enable pixels of the array of light sensitive pixels controlled by the row decoder based on the row-address signal and the enable signal. 
 
 
     
     
       22. The method of  claim 21  wherein the plurality of portions comprise at least one of:
 interlaced rows of pixels of the array of light-sensitive pixels; and 
 blocks of rows of pixels of the array of light-sensitive pixels. 
 
     
     
       23. The method of  claim 21  wherein the plurality of portions comprise at least one of:
 interlaced columns of pixels of the array of light-sensitive pixels; 
 interlaced columns and rows of pixels of the array of light-sensitive pixels; and 
 blocks of columns and rows of pixels of the array of light-sensitive pixels. 
 
     
     
       24. The method of  claim 21 , comprising at least one of:
 storing a photodiode charge for a first exposure to a first capacitor of a pixel and storing a reset noise charge associated with the first exposure to a second capacitor of the pixel; and 
 storing the photodiode charge for the first exposure to the first capacitor of the pixel and storing a photodiode charge for a second exposure to a second capacitor of the pixel. 
 
     
     
       25. The method of  claim 21 , comprising:
 controlling a plurality of illumination sources during the capturing of the plurality of image exposures.