Semiconductor memory device and weak cell detection method thereof

Abstract

A semiconductor memory device includes: a plurality of memory blocks; a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and a weak cell detection circuit suitable for compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data during the test mode.

What is claimed is: 
     
       1. A semiconductor memory device comprising:
 a plurality of memory blocks; 
 a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; 
 a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and 
 a weak cell detection circuit suitable for compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data during the test mode. 
 
     
     
       2. The semiconductor memory device of  claim 1 ,
 wherein the plurality of the bit-line sense amplifiers are disposed in a first region, 
 the weak cell detection circuit is disposed in a second region, 
 the plurality of the memory blocks are disposed in a third region, 
 the word line driver is disposed are disposed in a fourth region, and 
 a pair of the first and second regions and a pair of third and fourth regions are alternately disposed in a first direction. 
 
     
     
       3. The semiconductor memory device of  claim 2 , wherein the second region is a sub-hole region. 
     
     
       4. The semiconductor memory device of  claim 1 ,
 wherein the weak cell detection circuit includes a plurality of weak cell detectors that correspond to the plurality of the bit-line sense amplifiers, respectively, and 
 each of the plurality of the weak cell detectors compresses a data provided through a corresponding one among the plurality of segment data lines from a corresponding bit-line sense amplifier for generating a compressed data, and transfer the compressed data to a corresponding one among a plurality of local data lines during the test mode. 
 
     
     
       5. The semiconductor memory device of  claim 4 , wherein each of the plurality of the weak cell detectors includes:
 a data compression unit suitable for compressing the data transferred through the corresponding segment data line from the corresponding bit-line sense amplifier for generating the compressed data; and 
 a local line mapping unit operable during the test mode, and suitable for outputting the compressed data to the corresponding local data line. 
 
     
     
       6. The semiconductor memory device of  claim 1 ,
 wherein the weak cell detection circuit includes a plurality of data compression units serially coupled to each other, and respectively corresponding to the plurality of the bit-line sense amplifiers, and 
 wherein the weak cell detection circuit outputs as a final test result a compressed data from the data compression unit of a final stage among the plurality of data compression units. 
 
     
     
       7. The semiconductor memory device of  claim 6 ,
 wherein each of the plurality of the data compression units compresses a data provided through a corresponding one among the plurality segment data line from a corresponding bit-line sense amplifier with a compressed data provided from one among the other data compression units for generating a compressed data of its own. 
 
     
     
       8. The semiconductor memory device of  claim 6 , wherein one or more weak cell detection circuits corresponding to the memory blocks that do not share the bit-line sense amplifiers further transfer the compressed data of their own to corresponding ones among a plurality of local data lines during the test mode. 
     
     
       9. The semiconductor memory device of  claim 1 , wherein the weak cell detection circuit includes:
 a plurality of data compression units respectively corresponding to the plurality of the bit-line sense amplifiers, each data compression unit being suitable for compressing data provided through a corresponding one among the plurality of segment data lines from a corresponding bit-line sense amplifier for generating a compressed data; and 
 a shift register suitable for simultaneously storing a plurality of the compressed data provided from the plurality of data compression units, and sequentially outputting the plurality of the compressed data in response to a shift signal. 
 
     
     
       10. The semiconductor memory device of  claim 9 , wherein the plurality of the data compression units are disposed in a sub-hole region, and the shift register is disposed in an X-hole region. 
     
     
       11. A semiconductor memory device comprising:
 a plurality of memory blocks; 
 a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, and suitable for sensing and amplifying data read from memory cells coupled to activated word lines through bit lines, and outputting the amplified data as first amplified data through a plurality of segment data lines; 
 a plurality of local sense amplifiers each suitable for sensing and amplifying a corresponding one of the first amplified data transferred through a corresponding one of the plurality of the segment data lines, and outputting the amplified first amplified data as second amplified data through a plurality of local data lines; 
 a word line driver suitable for activating word lines of memory blocks that do not share the bit-line sense amplifiers during a test mode; and 
 a plurality of weak cell detectors corresponding to the plurality of the bit-line sense amplifiers, respectively, 
 wherein each of the plurality of the weak cell detectors compresses the corresponding one of the first amplified data transferred through the corresponding one of the plurality of the segment data lines from a corresponding one of the plurality of bit-line sense amplifiers for generating and output a compressed data to a corresponding one among the plurality of the local data lines during the test mode. 
 
     
     
       12. The semiconductor memory device of  claim 11 ,
 wherein the plurality of the bit-line sense amplifiers are disposed in a first region, 
 the weak cell detection circuit is disposed in a second region, 
 the plurality of the memory blocks are disposed in a third region, 
 the word line driver is disposed are disposed in a fourth region, and 
 a pair of the first and second regions and a pair of third and fourth regions are alternately disposed in a first direction. 
 
     
     
       13. The semiconductor memory device of  claim 12 , wherein the second region is a sub-hole region. 
     
     
       14. The semiconductor memory device of  claim 11 , wherein each of the plurality of the weak cell detectors includes:
 a data compression unit suitable for compressing the data transferred through the corresponding segment data line from the corresponding bit-line sense amplifier for generating the compressed data; and 
 a local line mapping unit operable during the test mode, and suitable for outputting the compressed data to the corresponding local data line. 
 
     
     
       15. A method for detecting a weak cell in a semiconductor memory device which includes a plurality of memory blocks and a plurality of bit-line sense amplifiers shared by neighboring memory blocks among the plurality of the memory blocks, comprising:
 activating word lines of memory blocks that do not share the bit-line sense amplifiers among the plurality of the memory blocks; 
 sensing and amplifying data transferred from memory cells coupled to the activated word lines through bit lines, and outputting the amplified data through a plurality of segment data lines; and 
 compressing the amplified data transferred through the plurality of the segment data lines for generating compressed data and detecting a weak cell based on the compressed data. 
 
     
     
       16. The method of  claim 15 , wherein the detecting of the weak cell includes outputting the compressed data to a plurality of local data lines. 
     
     
       17. The method of  claim 16 ,
 wherein the compressing of the amplified data includes compressing the amplified data transferred from a corresponding one among the plurality of bit-line sense amplifiers through a corresponding one among the segment data lines, and 
 the outputting of the compressed data includes outputting the compressed data to corresponding one among the plurality of local data lines. 
 
     
     
       18. The method of  claim 15 ,
 wherein the compressing of the amplified data includes compressing a data provided through a corresponding one among the plurality segment data lines from a corresponding bit-line sense amplifier with a compressed data provided from one among the other bit-line sense amplifiers for generating a second compressed data. 
 
     
     
       19. The method of  claim 15 ,
 wherein the compressing of the amplified data includes compressing data provided through a corresponding one among the plurality of segment data lines from a corresponding bit-line sense amplifier for generating a plurality of compressed data and outputting the plurality of the compressed data; and 
 the outputting of the compressed data includes simultaneously storing the plurality of the compressed data and sequentially outputting the plurality of the compressed data in response to a shift signal.