Current detection circuit

Abstract

To provide a current detection circuit which suppresses a change in characteristics of a PMOS transistor on the non-inversion input terminal side of a differential amplifier due to NBTI and causes no change in threshold value at which an output voltage of the current detection circuit is inverted. A voltage limiting circuit which limits a voltage drop is provided between a non-inversion input terminal of a differential amplifier and a source of a PMOS transistor on the inversion input terminal side.

What is claimed is: 
     
       1. A current detection circuit comprising:
 a sense resistor provided in a power supply line; and 
 a differential amplifier which detects a current flowing through the power supply line by a voltage across the sense resistor, 
 wherein the sense resistor is connected to an inversion input terminal and a non-inversion input terminal of the differential amplifier at both ends, 
 wherein the differential amplifier includes a first resistor, a first PMOS transistor, and a first current source which are connected in series between the inversion input terminal and GND, 
 wherein the differential amplifier includes a second resistor, a second PMOS transistor, and a second current source which are connected in series between the non-inversion input terminal and GND, 
 wherein the first PMOS transistor has a gate and a drain connected to a gate of the second PMOS transistor, 
 wherein the second PMOS transistor has a drain connected to an output terminal of the differential amplifier, and 
 wherein a voltage limiting circuit which limits a voltage drop is provided between the non-inversion input terminal and a source of the first PMOS transistor. 
 
     
     
       2. The current detection circuit according to  claim 1 , wherein the voltage limiting circuit is an NMOS transistor which has a gate and a drain connected to the non-inversion input terminal, and a source connected to the source of the first PMOS transistor. 
     
     
       3. The current detection circuit according to  claim 1 , wherein the voltage limiting circuit is a third PMOS transistor which has a source connected to the non-inversion input terminal, and a gate and a drain connected to the source of the first PMOS transistor.