Memory test system and method of testing memory device

Abstract

A memory test system may include a tester and N memory devices, where N is a positive integer greater than 1. The tester may generate test signals. A K-th memory device of the N memory devices includes a plurality of K-th memory banks and a K-th decoder, where K is each positive integer equal to or smaller than N. The K-th memory banks may be configured to operate based on first internal signals and each of the K-th memory banks includes a plurality of unit blocks. The K-th decoder may be configured to convert the test signals corresponding to the first test to the first internal signals based on a K-th conversion relation and update the K-th conversion relation based on a result of the first test with respect to the K-th memory device.

What is claimed is: 
     
       1. A memory test system comprising:
 a tester configured to generate test signals; and 
 N memory devices, wherein a K-th memory device of the N memory devices comprises:
 a K-th decoder configured to, in a test mode, convert the test signals corresponding to a first test to first internal signals based on a K-th conversion relation, update the K-th conversion relation based on a result of the first test with respect to the K-th memory device, and convert the test signals corresponding to a second test to second internal signals based on the updated K-th conversion relation, where N is a positive integer greater than 1 and K is a positive integer equal to or smaller than N; and 
 a plurality of K-th memory banks configured to, in a test mode, operate based on the first and second internal signals, each of the K-th memory banks including a plurality of unit blocks. 
 
 
     
     
       2. The memory test system of  claim 1 , wherein first through N-th decoders of the N memory devices update first through N-th conversion relations respectively such that the second test for the N memory devices is performed in parallel, based on the first through N-th reset conversion relations, with respect to the respective memory banks that are determined through the first test to have errors. 
     
     
       3. The memory test system of  claim 1 , wherein the tester is configured to generate the test signals corresponding to the second test after the first test is finished and the K-th memory device performs the second test based on the updated K-th conversion relation. 
     
     
       4. The memory test system of  claim 3 , wherein each unit block of each bank of the K-th memory banks includes a plurality of memory cells, and
 wherein the second test is an additional test with respect to the each unit block including a greater number of failed memory cells than a reference number. 
 
     
     
       5. The memory test system of  claim 1 , wherein the K-th decoder includes a K-th register configured to store a K-th sub test result corresponding to the first test. 
     
     
       6. The memory test system of  claim 1 , wherein the K-th decoder updates the K-th conversion relation after the first test such that a bank enable signal of third internal signals by converting the test signals is deactivated when a repair command signal of the test signals is transferred to the K-th memory device that includes a number of failed unit blocks greater than a threshold number. 
     
     
       7. The memory test system of  claim 1 , wherein the K-th decoder updates the K-th conversion relation such that a K-th bank enable signal of the second internal signals is activated based on a repair command signal of the test signals, and the K-th memory device that includes a number of failed unit blocks in each of the K-th memory banks less than a threshold number and repairs the failed unit blocks. 
     
     
       8. A memory system comprising:
 a tester configured to generate test signals; and 
 first and second memory devices each device comprising:
 a decoder configured to, in a test mode, convert a first test address of the test signals to a first internal address corresponding to a first test and convert the first test address to second internal address corresponding to a second test, wherein the second internal address is different from the first internal address; and 
 a plurality of memory banks each including a plurality of memory cells, and configured to operate based on the first and second internal addresses in the test mode, 
 wherein the first test address is converted to the second internal address based on a result of the first test. 
 
 
     
     
       9. The memory system of  claim 8 , wherein each of the first and second memory devices further includes a register configured to store a result of the corresponding first test. 
     
     
       10. The memory system of  claim 8 , wherein a corresponding decoder of the first and second memory devices is configured to convert the first test address to the second internal address when a unit block of at least one of the first and second memory devices includes a number of failed memory cells corresponding to the first test, and
 wherein the number of failed memory cells is equal to or greater than a reference number. 
 
     
     
       11. The memory system of  claim 8 , wherein, corresponding to the second test, a selected memory bank of the first memory device based on the first test address is located at a different relative location from a selected memory bank of the second memory device based on the first test address. 
     
     
       12. The memory system of  claim 8 , wherein a decoder of each of the first and second memory devices is configured to convert the first test address to the same first internal address corresponding to the first test. 
     
     
       13. The memory system of  claim 8 , wherein the decoder of each of the first and second memory devices is configured to convert the first test address to respective second internal addresses, and simultaneously select different relative unit blocks of the first and second memory devices based on the first test address. 
     
     
       14. The memory system of  claim 8 , wherein each of the first and second memory devices is configured to:
 repair failed first unit blocks of each of the memory banks based on a repair command received from the tester when a number of failed first unit blocks is less than a threshold number; and 
 not repair failed second unit blocks based on the repair command when a number of failed second unit blocks is equal to or greater than the threshold number. 
 
     
     
       15. A method of testing a memory device, the method comprising:
 preparing a tester and n memory devices to be tested, n being a positive integer greater than 1; 
 transferring test signals from the tester to the n memory devices; 
 performing a first test by converting first test signals of the test signals to a first set of corresponding internal signals for each of the n memory devices; and 
 performing a second test by converting the first test signals to a second set of corresponding internal signals for each of the n memory devices based on a result of the first test, 
 wherein, the second set of corresponding internal signals for a first memory device of the n memory devices is different from the second set of corresponding internal signals for a second memory device of the n memory devices. 
 
     
     
       16. The method of  claim 15 , further comprising:
 for each of the n memory devices, storing a result of the corresponding first test in a register of that memory device. 
 
     
     
       17. The method of  claim 15 , wherein the first test signals for each of the n memory devices include a bank address signal. 
     
     
       18. The method of  claim 15 , wherein performing the second test occurs when a unit block of at least one of the n memory devices includes a number of failed memory cells equal to or greater than a reference number. 
     
     
       19. The method of  claim 15 , wherein performing the second test includes selecting simultaneously a first unit block of a first memory device and a second unit block of a second memory device based on a first address signal of the test signals, and
 wherein the first and second unit blocks have different relative locations with respect to the first and second memory devices in which they are included. 
 
     
     
       20. The method of  claim 15 , wherein performing the second test includes:
 performing a repair operation for a first memory device based on a repair command received from the tester when a number of failed unit blocks of the first memory device is less than a threshold number; and 
 not performing a repair operation for a second memory device based on the repair command when a number of failed unit blocks of the second memory device is equal to or greater than the threshold number.