Electronic device and method for fabricating the same

Abstract

Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: a free layer comprising CoFeGeB alloy, and having a changeable magnetization direction that is perpendicular to the free layer; a tunnel barrier layer positioned over the free layer, and configured for enabling electron tunneling; a pinned layer positioned over the tunnel barrier layer, and having a pinned magnetization direction that is perpendicular to the pinned layer; and a bottom layer positioned under the free layer, and having a B2 structure to improve a perpendicular magnetic crystalline anisotropy of the free layer.

What is claimed is: 
     
       1. An electronic device comprising a semiconductor memory,
 wherein the semiconductor memory comprises: 
 a free layer comprising CoFeGeB alloy, and having a changeable magnetization direction that is perpendicular to the free layer; 
 a tunnel barrier layer positioned over the free layer, and configured for enabling electron tunneling; 
 a pinned layer positioned over the tunnel barrier layer, and having a pinned magnetization direction that is perpendicular to the pinned layer; and 
 a bottom layer positioned under the free layer and including a material having a caesium chloride (B2) structure and in direct contact with the CoFeGeB alloy to improve a perpendicular magnetic crystalline anisotropy of the free layer. 
 
     
     
       2. The electronic device of  claim 1 , wherein the bottom layer comprises an MgO layer. 
     
     
       3. The electronic device of  claim 1 , wherein the tunnel barrier layer and the bottom layer comprise a same material. 
     
     
       4. The electronic device of  claim 3 , wherein the bottom layer has a smaller thickness than the tunnel barrier layer. 
     
     
       5. The electronic device of  claim 1 , wherein a content of Ge contained in the CoFeGeB alloy is less than 10%. 
     
     
       6. The electronic device of  claim 1 , wherein the semiconductor memory further comprises a buffer layer positioned under the bottom layer, and having a BCC structure to promote crystal growth of the bottom layer. 
     
     
       7. The electronic device of  claim 6 , wherein the buffer layer comprises a CoFe layer. 
     
     
       8. The electronic device of  claim 1 , wherein the free layer, the tunnel barrier layer, and the pinned layer have sidewalls which are aligned with each other, and
 the bottom layer has sidewalls which are not aligned with the sidewalls of the free layer, the tunnel barrier layer, and the pinned layer. 
 
     
     
       9. The electronic device of  claim 8 , wherein the top surface of the bottom layer has a larger width than the bottom surface of the free layer. 
     
     
       10. The electronic device of  claim 6 , wherein the free layer, the tunnel barrier layer, and the pinned layer have sidewalls which are aligned with each other,
 the bottom layer and the buffer layer have sidewalls which are aligned with each other, and 
 the sidewalls of the free layer, the tunnel barrier layer, and the pinned layer are not aligned with the sidewalls of the bottom layer and the buffer layer. 
 
     
     
       11. The electronic device of  claim 1 , further comprising a microprocessor which includes:
 a control unit configured to receive a signal including a command from an outside of the microprocessor, and performs extracting, decoding of the command, or controlling input or output of a signal of the microprocessor; 
 an operation unit configured to perform an operation based on a result that the control unit decodes the command; and 
 a memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed, 
 wherein the semiconductor memory is part of the memory unit in the microprocessor. 
 
     
     
       12. The electronic device of  claim 1 , further comprising a processor which includes:
 a core unit configured to perform, based on a command inputted from an outside of the processor, an operation corresponding to the command, by using data; 
 a cache memory unit configured to store data for performing the operation, data corresponding to a result of performing the operation, or an address of data for which the operation is performed; and 
 a bus interface connected between the core unit and the cache memory unit, and configured to transmit data between the core unit and the cache memory unit,
 wherein the semiconductor memory is part of the cache memory unit in the processor. 
 
 
     
     
       13. The electronic device of  claim 1 , further comprising a processing system which includes:
 a processor configured to decode a command received by the processor and control an operation for information based on a result of decoding the command; 
 an auxiliary memory device configured to store a program for decoding the command and the information; 
 a main memory device configured to call and store the program and the information from the auxiliary memory device such that the processor can perform the operation using the program and the information when executing the program; and 
 an interface device configured to perform communication between at least one of the processor, the auxiliary memory device and the main memory device and the outside, 
 wherein the semiconductor memory is part of the auxiliary memory device or the main memory device in the processing system. 
 
     
     
       14. The electronic device of  claim 1 , further comprising a data storage system which includes:
 a storage device configured to store data and conserve stored data regardless of power supply; 
 a controller configured to control input and output of data to and from the storage device according to a command inputted form an outside; 
 a temporary storage device configured to temporarily store data exchanged between the storage device and the outside; and 
 an interface configured to perform communication between at least one of the storage device, the controller and the temporary storage device and the outside, 
 wherein the semiconductor memory is part of the storage device or the temporary storage device in the data storage system. 
 
     
     
       15. The electronic device of  claim 1 , further comprising a memory system which includes:
 a memory configured to store data and conserve stored data regardless of power supply; 
 a memory controller configured to control input and output of data to and from the memory according to a command inputted form an outside; 
 a buffer memory configured to buffer data exchanged between the memory and the outside; and 
 an interface configured to perform communication between at least one of the memory, the memory controller and the buffer memory and the outside, 
 wherein the semiconductor memory is part of the memory or the buffer memory in the memory system. 
 
     
     
       16. The electronic device of  claim 1 , further comprising a magnetic correction layer positioned over the pinned layer and including a magnetization direction anti-parallel to that of the pinned layer. 
     
     
       17. The electronic device of  claim 16 , further comprising a spacer layer interposed between the magnetic correction layer and the pinned layer and including a metal. 
     
     
       18. The electronic device of  claim 1 , wherein the bottom layer has a crystalline structure in a (001) direction. 
     
     
       19. The electronic device of  claim 1 , wherein the tunnel barrier layer includes an MgO layer.