P
US9871513B2ActiveUtilityPatentIndex 71

Semiconductor device

Assignee: FUJI ELECTRIC CO LTDPriority: Jun 10, 2015Filed: May 10, 2016Granted: Jan 16, 2018
Est. expiryJun 10, 2035(~8.9 yrs left)· nominal 20-yr term from priority
Inventors:IWAMIZU MORIOYOSHIDA YASUKI
H03K 17/0822H03K 17/687H03K 17/08104H03K 17/284H02P 1/16H03K 17/08122H03K 17/08112H03K 5/08H03K 2217/0081H02P 31/00H02M 3/07
71
PatentIndex Score
5
Cited by
11
References
11
Claims

Abstract

In activating a motor, a gate voltage with which a power semiconductor element may supply a rush current of the motor is generated by a charge pump circuit, when a certain time (time until the rush current ends) has elapsed after activating the motor, a timer circuit operates a gate clamp circuit, which reduces the gate voltage of the power semiconductor element to reduce the current-carrying capability of the power semiconductor element. Subsequently, when the motor has caused a short-circuit failure, the power semiconductor element, because its gate voltage is reduced by the gate clamp circuit in advance, supplies only a load short current corresponding to the reduced gate voltage. Accordingly, the heat generation due to the short-circuit current is also small and an increase in temperature is also suppressed.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
       1. A semiconductor device comprising
 a driver circuit configured to drive a power semiconductor element, the driver circuit including: 
 a gate clamp circuit configured to clamp a gate voltage of the power semiconductor element; 
 a timer circuit configured to start counting when a current starts flowing in the power semiconductor element; and 
 an extracting transistor having a first terminal connected to a gate of the semiconductor element and having a second terminal connected to a terminal of the semiconductor element and an output of the gate clamp circuit, the extracting transistor configured to be controlled to reduce a switching time of the semiconductor element, 
 wherein the timer circuit is configured to operate the gate clamp circuit after a certain time from the start of the counting of the timer circuit so as to reduce current-carrying capability of the power semiconductor element. 
 
     
     
       2. The semiconductor device according to  claim 1 , wherein the certain time is set to correspond to a duration of a rush current, such that the certain time is set to extend past an end of the duration of the rush current. 
     
     
       3. The semiconductor device according to  claim 2 , wherein the driver circuit further includes a booster circuit configured to generate the gate voltage when the power semiconductor element is turned on. 
     
     
       4. The semiconductor device according to  claim 3 , wherein the booster circuit is a charge pump circuit. 
     
     
       5. The semiconductor device according to  claim 4 , wherein the charge pump circuit includes an oscillator and a multi-stage booster section configured to output the gate voltage that is boosted by a switching operation by an oscillation signal of the oscillator. 
     
     
       6. The semiconductor device according to  claim 5 , wherein the gate clamp circuit is a circuit configured to reduce the gate voltage by reducing a number of stages of the multi-stage booster section based on a signal from the timer circuit. 
     
     
       7. The semiconductor device according to  claim 5 , wherein the gate clamp circuit is a circuit configured to reduce the gate voltage by reducing an oscillation frequency of the oscillator based on a signal from the timer circuit. 
     
     
       8. The semiconductor device according to  claim 1  integrally comprising the power semiconductor element together with the driver circuit. 
     
     
       9. The semiconductor device according to  claim 1 , wherein the gate clamp circuit comprises a transistor,
 an output of the timer circuit is connected to a gate of the transistor of the gate clamp circuit, and 
 the timer circuit is configured to operate the gate clamp circuit by asserting a signal at the gate of the transistor of the gate clamp circuit after the certain time from the start of the counting of the timer circuit. 
 
     
     
       10. The semiconductor device according to  claim 9 , wherein the gate clamp circuit further comprises a plurality of diodes connected in series, wherein one terminal of the transistor of the gate clamp circuit is connected to an end of one of the diodes among the plurality of diodes, and another terminal of the transistor is connected to an output terminal of the semiconductor device. 
     
     
       11. The semiconductor element according to  claim 7 , wherein the oscillator comprises a plurality of inverters connected in series, one terminal of the transistor of the gate clamp circuit is connected between two of the plurality of transistors, and another terminal of the transistor of the gate clamp circuit is connected to ground.

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