Single-wire communications using iterative baud learning

Abstract

Systems and techniques for single-wire communications are described. A described technique includes detecting transitions on a single-wire bus that are produced by a host device, determining an estimated baud rate of the host device based on the transition, and communicating with the host device based on the estimated baud rate. Determining the estimated baud rate can include charging a capacitor based on a charging rate in response to a detection of a first transition of the transitions, sampling a capacitor voltage associated with the capacitor in response to a detection of a second transition of the transitions, and adjusting the charging rate based on a comparison between the capacitor voltage and a reference voltage.

What is claimed is: 
     
       1. A device comprising:
 a detector to detect transitions on a single-wire bus that are produced by a host; 
 a timing estimator to determine an estimated baud rate of the host based on the transitions, wherein the timing estimator is configured to charge a capacitor based on a charging rate in response to a detection of a first transition of the transitions, sample a capacitor voltage associated with the capacitor in response to a detection of a second transition of the transitions, and adjust the charging rate based on a comparison between the capacitor voltage and a reference voltage; and 
 circuitry to communicate with the host based on the estimated baud rate. 
 
     
     
       2. The device of  claim 1 , wherein the timing estimator is configured to adjust the charging rate by increasing the charging rate if the capacitor voltage is less than the reference voltage, and wherein the timing estimator is configured to adjust the charging rate by decreasing the charging rate if the capacitor voltage is not less than the reference voltage. 
     
     
       3. The device of  claim 1 , comprising:
 a transistor coupled with the capacitor, 
 wherein the timing estimator is configured to reset the capacitor by switching on the transistor to discharge the capacitor. 
 
     
     
       4. The device of  claim 1 , wherein the timing estimator is configured to determine the estimated baud rate by controlling the charging rate of the capacitor based on a control register comprising a plurality of bits arranged from a most significant bit to a least significant bit. 
     
     
       5. The device of  claim 4 , wherein the timing estimator is configured to iteratively adjust the charging rate via determining bit-by-bit each of the bits of the control register through successive ones of the transitions by starting with the most significant bit and ending with the least significant bit. 
     
     
       6. The device of  claim 1 , wherein the transitions comprise falling edge transitions. 
     
     
       7. The device of  claim 1 , comprising:
 a non-volatile memory structure; and 
 a processor configured to perform an operation responsive to a command received over the single-wire bus, wherein the operation comprises retrieving data from the non-volatile memory structure in response to the command, and wherein the processor is configured to cause the data to be transmitted to the host based on the estimated baud rate. 
 
     
     
       8. A method comprising:
 detecting transitions on a single-wire bus that are produced by a host device; 
 determining an estimated baud rate of the host device based on the transitions, wherein determining the estimated baud rate comprises charging a capacitor based on a charging rate in response to a detection of a first transition of the transitions, sampling a capacitor voltage associated with the capacitor in response to a detection of a second transition of the transitions, and adjusting the charging rate based on a comparison between the capacitor voltage and a reference voltage; and 
 communicating with the host device based on the estimated baud rate. 
 
     
     
       9. The method of  claim 8 , wherein adjusting the charging rate comprises:
 increasing the charging rate if the capacitor voltage is less than the reference voltage; and 
 decreasing the charging rate if the capacitor voltage is not less than the reference voltage. 
 
     
     
       10. The method of  claim 8 , wherein determining the estimated baud rate comprises switching on a transistor to discharge the capacitor in response to the detection of the first transition of the transitions. 
     
     
       11. The method of  claim 8 , wherein determining the estimated baud rate comprises controlling the charging rate of the capacitor based on a control register comprising a plurality of bits arranged from a most significant bit to a least significant bit. 
     
     
       12. The method of  claim 11 , wherein determining the estimated baud rate comprises determining bit-by-bit each of the bits of the control register through successive ones of the transitions by starting with the most significant bit and ending with the least significant bit. 
     
     
       13. The method of  claim 8 , wherein the transitions comprise falling edge transitions. 
     
     
       14. A system comprising:
 a host device; and 
 a slave device coupled with the host device via a single-wire bus, wherein the slave device is configured to perform operations comprising:
 detecting transitions on the single-wire bus that are produced by the host device, 
 determining an estimated baud rate of the host device based on the transitions, wherein determining the estimated baud rate comprises charging a capacitor based on a charging rate in response to a detection of a first transition of the transitions, sampling a capacitor voltage associated with the capacitor in response to a detection of a second transition of the transitions, and adjusting the charging rate based on a comparison between the capacitor voltage and a reference voltage, and 
 communicating with the host device based on the estimated baud rate. 
 
 
     
     
       15. The system of  claim 14 , wherein adjusting the charging rate based on the comparison comprises:
 increasing the charging rate if the capacitor voltage is less than the reference voltage; and 
 decreasing the charging rate if the capacitor voltage is not less than the reference voltage. 
 
     
     
       16. The system of  claim 14 , wherein determining the estimated baud rate comprises switching on a transistor to discharge the capacitor in response to the detection of the first transition of the transitions. 
     
     
       17. The system of  claim 14 , wherein determining the estimated baud rate comprises controlling the charging rate of the capacitor based on a control register comprising a plurality of bits arranged from a most significant bit to a least significant bit. 
     
     
       18. The system of  claim 17 , wherein determining the estimated baud rate comprises determining bit-by-bit each of the bits of the control register through successive ones of the transitions by starting with the most significant bit and ending with the least significant bit. 
     
     
       19. The system of  claim 14 , wherein the transitions comprise falling edge transitions. 
     
     
       20. The system of  claim 14 , wherein the slave device comprises:
 a non-volatile memory structure; and 
 a processor configured to perform an operation responsive to a command received over the single-wire bus, wherein the operation comprises retrieving data from the non-volatile memory structure in response to the command, and wherein the processor is configured to cause the data to be transmitted to the host device based on the estimated baud rate.