Semiconductor device for reducing an instantaneous voltage drop

Abstract

A semiconductor device for reducing an instantaneous voltage drop is provided. The semiconductor device includes a first power line configured to provide a first power supply voltage and a first power transistor connected between the first power line and a first logic transistor. The first power transistor includes a first source or drain connected to the first power line, a gate receiving a power gating control signal, and a second source or drain connected to a first source or drain of the first logic transistor using a shared semiconductor junction.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a power line configured to provide a power supply voltage; 
 a first logic transistor including a first gate, a first source and a first drain; 
 a second logic transistor connected to the first logic transistor, and including a second gate, a second source and a second drain; 
 a third logic transistor connected to the second logic transistor, and including a third gate, a third source and a third drain; 
 a first power transistor connected between the power line and the first logic transistor, the first power transistor including a fourth gate, a fourth source and a fourth drain; and 
 a second power transistor connected between the power line and the third logic transistor, 
 wherein the power line is connected to one of the fourth source and the fourth drain, 
 one of the first source and the first drain is connected to the other of the fourth source and the fourth drain, using a first shared semiconductor junction, 
 the fourth gate is configured to receive a power gating control signal, and 
 one of the third source and the third drain is connected to the second power transistor. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the second power transistor includes a fifth gate, a fifth source and a fifth drain, and
 the one of the third source and the third drain is connected one of the fifth source and the fifth drain, using a second shared semiconductor junction. 
 
     
     
       3. The semiconductor device of  claim 1 , wherein the other of the first source and the first drain is connected one of the second source and the second drain. 
     
     
       4. The semiconductor device of  claim 3 , wherein the other of the second source and the second drain is connected one of the other of the third source and the third drain. 
     
     
       5. The semiconductor device of  claim 1 , wherein the first power transistor and the second power transistor are connected in parallel with respect to the power line. 
     
     
       6. The semiconductor device of  claim 1 , wherein the first logic transistor, the second logic transistor and the third logic transistor are connected in series. 
     
     
       7. The semiconductor device of  claim 1 , wherein the first power transistor is a P-channel metal-oxide semiconductor (PMOS) transistor, and
 the second power transistor is an N-channel metal-oxide semiconductor (NMOS) transistor. 
 
     
     
       8. The semiconductor device of  claim 1 , wherein the power line includes a metal line, a via, and a contact to provide the power supply voltage. 
     
     
       9. The semiconductor device of  claim 1 , wherein at least a part of the one of the first source and the first drain is placed in common with at least a part of the other of the fourth source and the fourth drain. 
     
     
       10. A semiconductor memory device comprising:
 a first power line configured to provide a first power supply voltage; 
 a second power line configured to provide a second power supply voltage; 
 a plurality of word lines extending in a first direction; 
 a plurality of bit line pairs extending in a second direction crossing the first direction; 
 a row decoder configured to select one of the plurality of word lines in response to an input row address signal; 
 a plurality of bit cells configured to store data, each of the plurality of bit cells being connected to one of the plurality of word lines and one of the plurality of bit line pairs; 
 an input/output (I/O) circuit including a first logic transistor, a second logic transistor, a first power transistor and a second power transistor, configured to receive the second power supply voltage and configured to generate output data; and 
 a power circuit configured to receive the first power supply voltage, and configured to cut off the second power supply voltage based on a power gating control signal, 
 wherein the first logic transistor is connected to the first power transistor using a first shared semiconductor junction, and 
 the second logic transistor is connected to the second power transistor using a second shared semiconductor junction. 
 
     
     
       11. The semiconductor memory device of  claim 10 , wherein the first logic transistor includes a first gate, a first source and a first drain,
 the second logic transistor includes a second gate, a second source and a second drain, 
 the first power transistor is connected between the first power line and the first logic transistor, the first power transistor including a third gate, a third source and a third drain, and 
 the second power transistor is connected between the first power line and the second logic transistor. 
 
     
     
       12. The semiconductor memory device of  claim 11 , wherein the first power line is connected to one of the third source and the third drain,
 one of the first source and the first drain is connected to the other of the third source and the third drain, using the first shared semiconductor junction, 
 the third gate is configured to receive the power gating control signal, and 
 one of the second source and the second drain is connected to the second power transistor. 
 
     
     
       13. The semiconductor memory device of  claim 12 , wherein the second power transistor includes a fourth gate, a fourth source and a fourth drain, and
 the one of the second source and the second drain is connected one of the fourth source and the fourth drain, using the second shared semiconductor junction. 
 
     
     
       14. The semiconductor memory device of  claim 10 , wherein the first power transistor and the second power transistor are connected in parallel with respect to the first power line. 
     
     
       15. The semiconductor device of  claim 10 , wherein the first power transistor is a P-channel metal-oxide semiconductor (PMOS) transistor, and
 the second power transistor is an N-channel metal-oxide semiconductor (NMOS) transistor. 
 
     
     
       16. A semiconductor device comprising:
 a substrate; 
 an active region formed in the substrate; 
 a first source/drain, a second source/drain and a third source/drain formed in the active region; 
 a first gate formed between the first source/drain and the second source/drain; and 
 a second gate formed between the second source/drain and the third source/drain, 
 wherein the first gate, the first source/drain and the second source/drain form a first power transistor, 
 the second gate, the second source/drain and the third source/drain form a first logic transistor included in a precharge circuit, and 
 a power line is connected to the first source/drain, 
 wherein the second source/drain is formed in common for the first power transistor and for the first logic transistor, using a shared semiconductor junction, and 
 a fifth source/drain is formed in common for a second power transistor and for a third logic transistor, using the shared semiconductor junction. 
 
     
     
       17. The semiconductor device of  claim 16 , wherein a ratio of width to length of the first source/drain is different from a ratio of width to length of the third source/drain. 
     
     
       18. The semiconductor device of  claim 17 , wherein the ratio of width to length of the first source/drain is at least two times of the ratio of width to length of the third source/drain. 
     
     
       19. The semiconductor device of  claim 16 , further comprising:
 a fourth source/drain, the fifth source/drain and a sixth source/drain formed in the active region; 
 a third gate formed between the third source/drain and the fourth source/drain; 
 a fourth gate formed between the fourth source/drain and the fifth source/drain; and 
 a fifth gate formed between the fifth source/drain and the sixth source/drain, 
 wherein the third gate, the third source/drain and the fourth source/drain form a second logic transistor, 
 the fourth gate, the fourth source/drain and the fifth source/drain form the third logic transistor, 
 the fifth gate, the fifth source/drain and the sixth source/drain form the second power transistor, 
 a ratio of width to length of the fourth source/drain is different from a ratio of width to length of the sixth source/drain, and 
 the power line is connected to the sixth source/drain. 
 
     
     
       20. The semiconductor device of  claim 16 , wherein the second source/drain is formed in common for the first power transistor and for the first logic transistor, using a shared semiconductor junction, and
 the fifth source/drain is formed in common for the second power transistor and for the third logic transistor, using a shared semiconductor junction.