Spatially decoupled floating gate semiconductor device

Abstract

A method includes forming a tunneling dielectric layer on a semiconductor substrate, a first portion of the tunneling dielectric layer is directly above a channel region in the semiconductor substrate and a second portion of the tunneling dielectric layer is directly above source-drain regions located on opposing sides of the channel region, the second portion of the tunneling dielectric layer is thicker than the first portion of the tunneling dielectric layer, forming a floating gate directly above the first portion of the tunneling dielectric layer and the second portion of the tunneling dielectric layer, and forming a control dielectric layer directly above the floating gate.

The invention claimed is: 
     
       1. A method comprising:
 providing a semiconductor substrate comprising a source-drain region on opposite sides of a channel region; 
 forming a first dielectric layer above and in direct contact with the source-drain region and the channel region; 
 forming a second dielectric layer above and in direct contact with the first dielectric layer, wherein the second dielectric layer has a higher etch rate than the first dielectric layer; 
 removing a portion of the second dielectric layer above a portion of the first dielectric in direct contact with the channel region, 
 wherein the portion of the first dielectric layer in direct contact with the channel region comprises a thin region, and 
 wherein a remaining portion of the second dielectric layer above the first dielectric layer and the source-drain region comprises a thick region; 
 forming a floating gate above and in direct contact with the thin region and the thick region; 
 implanting the floating gate with elements having an energy bandgap lower than that of the floating gate in a continuous gradient such that an energy band gap of the floating gate is reduced in a tapered fashion along a longitudinal direction parallel to the channel region; and 
 forming a control dielectric layer directly above the floating gate. 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming a control gate directly above the control dielectric layer. 
 
     
     
       3. The method of  claim 1 , wherein a portion of the floating gate above and in direct contact with the thin region comprises a program/erase region of the floating gate. 
     
     
       4. The method of  claim 1 , wherein another portion of the floating gate above and in direct contact with the thick region comprises a charge retention region of the floating gate. 
     
     
       5. The method of  claim 1 , wherein
 a bandgap difference between the floating gate and the thin region and the floating gate and the thick region increases continuously in the longitudinal direction parallel to the channel region from the thin region to the thick region, 
 wherein the bandgap difference increases charge carriers movement from the thin region to the thick region. 
 
     
     
       6. The method of  claim 1 , wherein the thin region has a thickness varying from approximately 1 nm to approximately 5 nm. 
     
     
       7. The method of  claim 1 , wherein the thick region has a thickness varying from approximately 6 nm to approximately 20 nm. 
     
     
       8. The method of  claim 1 , wherein the second dielectric layer comprises a lower density and higher structural defects than the first dielectric layer. 
     
     
       9. The method of  claim 1 , further comprising:
 annealing the floating gate to facilitate inter-diffusion of implanted elements. 
 
     
     
       10. A method of forming a semiconductor device, the method comprising:
 forming a first dielectric layer above and in direct contact with a source-drain region and a channel region; 
 forming a second dielectric layer above and in direct contact with the first dielectric layer, wherein the second dielectric layer has a higher etch rate than the first dielectric layer; 
 removing a portion of the second dielectric layer above a portion of the first dielectric in direct contact with the channel region, 
 wherein the portion of the first dielectric layer in direct contact with the channel region comprises a thin region, and 
 wherein a remaining portion of the second dielectric layer above the first dielectric layer and the source-drain region comprises a thick region; 
 forming a floating gate above and in direct contact with the thin region and the thick region; and 
 implanting the floating gate with elements having an energy bandgap lower than that of the floating gate in a continuous gradient such that an energy band gap of the floating gate is reduced in a tapered fashion along a longitudinal direction parallel to the channel region. 
 
     
     
       11. The method of  claim 1 , further comprising:
 forming a control dielectric layer directly above the floating gate; and 
 forming a control gate directly above the control dielectric layer. 
 
     
     
       12. The method of  claim 1 , wherein a portion of the floating gate above and in direct contact with the thin region comprises a program/erase region of the floating gate. 
     
     
       13. The method of  claim 1 , wherein another portion of the floating gate above and in direct contact with the thick region comprises a charge retention region of the floating gate. 
     
     
       14. The method of  claim 1 , wherein a bandgap difference between the floating gate and the thin region and the floating gate and the thick region increases continuously in the longitudinal direction parallel to the channel region from the thin region to the thick region,
 wherein the bandgap difference increases charge carriers movement from the thin region to the thick region. 
 
     
     
       15. The method of  claim 1 , wherein the second dielectric layer comprises a lower density and higher structural defects than the first dielectric layer. 
     
     
       16. The method of  claim 1 , further comprising:
 annealing the floating gate to facilitate inter-diffusion of implanted elements. 
 
     
     
       17. A method of forming a semiconductor device, the method comprising:
 providing a semiconductor substrate comprising a source-drain region on opposite sides of a channel region; 
 forming a first dielectric layer above and in direct contact with the source-drain region and the channel region; 
 forming a second dielectric layer above and in direct contact with the first dielectric layer, wherein the second dielectric layer has a higher etch rate than the first dielectric layer; 
 removing a portion of the second dielectric layer above a portion of the first dielectric in direct contact with the channel region, 
 wherein the portion of the first dielectric layer in direct contact with the channel region comprises a thin region, and 
 wherein a remaining portion of the second dielectric layer above the first dielectric layer and the source-drain region comprises a thick region; 
 forming a floating gate above and in direct contact with the thin region and the thick region; 
 implanting the floating gate with elements having an energy bandgap lower than that of the floating gate in a continuous gradient such that an energy band gap of the floating gate is reduced in a tapered fashion along a longitudinal direction parallel to the channel region, 
 wherein a bandgap difference between the floating gate and the thin region and the floating gate and the thick region increases continuously in the longitudinal direction parallel to the channel region from the thin region to the thick region such that charge carriers movement increases from the thin region to the thick region; and 
 annealing the floating gate to facilitate inter-diffusion of implanted elements; and 
 forming a control dielectric layer directly above the floating gate. 
 
     
     
       18. The method of  claim 1 , wherein a portion of the floating gate above and in direct contact with the thin region comprises a program/erase region of the floating gate. 
     
     
       19. The method of  claim 1 , wherein another portion of the floating gate above and in direct contact with the thick region comprises a charge retention region of the floating gate. 
     
     
       20. The method of  claim 1 , wherein the second dielectric layer comprises a lower density and higher structural defects than the first dielectric layer.