Dicing method for wafer-level packaging and semiconductor chip with dicing structure adapted for wafer-level packaging

Abstract

A semiconductor substrate ( 1 ) is provided with integrated circuits. Dicing trenches ( 7 ) are formed in the substrate ( 1 ) between the integrated circuits, a polyimide layer ( 8 ) spanning the trenches ( 7 ) is applied above the integrated circuits, a tape layer ( 14 ) is applied above the polyimide layer ( 8 ), and a layer portion of the substrate ( 1 ) is removed from the substrate side ( 17 ) opposite the tape layer ( 14 ), until the trenches ( 7 ) are opened and dicing of the substrate ( 1 ) is thus effected. The polyimide layer ( 8 ) is severed in sections ( 18 ) above the trenches ( 7 ) when the tape layer ( 14 ) is removed. The semiconductor chip is provided with a cover layer ( 11 ) laterally confining the polyimide layer ( 8 ) near the trenches ( 7 ), in particular for forming breaking delimitations ( 9 ).

The invention claimed is: 
     
       1. A dicing method for wafer-level packaging, comprising:
 providing a semiconductor substrate with integrated circuit regions; 
 forming trenches in the substrate between the integrated circuit regions; 
 applying a tape layer above the integrated circuit regions and above the trenches; 
 removing a layer portion of the substrate from a substrate side opposite the tape layer, until the trenches are opened and dicing of the substrate is thus effected; 
 removing the tape layer; 
 after the formation of the trenches, applying a polyimide layer above the integrated circuit regions and above the trenches before the tape layer is applied; and 
 the polyimide layer being severed above the trenches when the tape layer is removed, 
 wherein the polyimide layer is provided with breaking delimitations near the trenches, 
 wherein the polyimide layer is photosensitive, and 
 wherein the breaking delimitations are formed using photolithography. 
 
     
     
       2. The dicing method of  claim 1 , wherein the polyimide layer is applied as a dry film spanning the trenches. 
     
     
       3. The dicing method of  claim 1 , wherein the breaking delimitations are formed by gaps in the polyimide layer. 
     
     
       4. The dicing method of  claim 1 , further comprising:
 the integrated circuit regions being provided with contact pads, which are not covered by the polyimide layer; and 
 bump contacts being applied before the tape layer is applied, each bump contact being electrically connected with one of the contact pads. 
 
     
     
       5. A dicing method for wafer-level packaging, comprising:
 providing a semiconductor substrate with integrated circuit regions; 
 forming trenches in the substrate between the integrated circuit regions; 
 applying a tape layer above the integrated circuit regions and above the trenches; 
 removing a layer portion of the substrate from a substrate side opposite the tape layer, until the trenches are opened and dicing of the substrate is thus effected; 
 removing the tape layer; 
 after the formation of the trenches, applying a polyimide layer above the integrated circuit regions and above the trenches before the tape layer is applied; 
 the polyimide layer being severed above the trenches when the tape layer is removed; 
 the integrated circuit regions being provided with contact pads, which are not covered by the polyimide layer; 
 bump contacts being applied before the tape layer is applied, each bump contact being electrically connected with one of the contact pads; 
 an electrically conductive layer being applied on the polyimide layer, sections of the electrically conductive layer contacting the contact pads; 
 a cover layer being applied on the electrically conductive layer, areas of the electrically conductive layer not being covered by the cover layer; 
 underbump metallizations and the bump contacts being applied on the uncovered areas of the electrically conductive layer before the tape layer is applied; and 
 the tape layer being applied on the cover layer. 
 
     
     
       6. The dicing method of  claim 5 , wherein the cover layer is applied by spinning a liquid polyimide layer on. 
     
     
       7. The dicing method of  claim 1 , further comprising:
 applying a dicing foil to the semiconductor substrate after the trenches are opened and before the tape layer is removed, the dicing foil being so flexible as to allow the polyimide layer to be severed by breaking. 
 
     
     
       8. The dicing method of  claim 4 , further comprising:
 an electrically conductive layer being applied on the polyimide layer, sections of the electrically conductive layer contacting the contact pads; 
 a cover layer being applied on the electrically conductive layer, areas of the electrically conductive layer not being covered by the cover layer; 
 underbump metallizations and the bump contacts being applied on the uncovered areas of the electrically conductive layer before the tape layer is applied; and 
 the tape layer being applied on the cover layer. 
 
     
     
       9. The dicing method of  claim 5 , wherein the polyimide layer is applied as a dry film spanning the trenches. 
     
     
       10. The dicing method of  claim 5 , further comprising:
 applying a dicing foil to the semiconductor substrate after the trenches are opened and before the tape layer is removed, the dicing foil being so flexible as to allow the polyimide layer to be severed by breaking.