Monitoring serial link errors

Abstract

A serial link data monitoring apparatus for targeting a given Bit Error Rate (BER) for stable serial link data communication is disclosed. An interface unit may be configured to receive data via a serial interface, and circuitry may be configured to monitor errors in the data. The circuitry may be further configured to perform one or more first training operations in response to a determination that the number of errors detected in the data is greater than a first threshold value, and perform a second training operation in response to a determination that a number of first training operations performed in a predetermined period of time is greater than a second threshold value. An amount of time to perform the second training operation may be greater than an amount of time to perform a given one of the first training operations.

What is claimed is: 
     
       1. An, apparatus, comprising:
 a serializer circuit configured to transmit, via a communication channel, a data stream including multiple data words, wherein a particular data word includes a plurality of data bits and a header; 
 a deserializer circuit configured to:
 receive the data stream via the communication channel; 
 determine a number of errors during reception of a given data word of the multiple data words; 
 in response to a detection of an end of the given data word:
 initiate a first training operation to adjust a sampling point, in response to a determination that the number of errors is greater than a threshold number of errors; and 
 initiate a second training operation to adjust the sampling point, in response to a determination that a number of first training operations previously performed during a particular period of time is greater than a threshold number of previously performed first training operations; and 
 
 
 wherein the serializer circuit is further configured to transmit a first number of training data bits during the first training operation and transmit a second number of training data bits during the second training operation, wherein the second number of training data bits is greater than the first number of training data bits. 
 
     
     
       2. The apparatus of  claim 1 , wherein to determine the number of errors during the reception of the plurality of data bits, the deserializer circuit is further configured to perform a Cyclic Redundancy Check (CRC). 
     
     
       3. The apparatus of  claim 1 , wherein to determine the number of errors during the reception of the plurality of data bits, the deserializer circuit is further configured to increment a first counter in response to detecting an error in the reception of the plurality of data bits in a given time period. 
     
     
       4. The apparatus of  claim 3 , wherein the deserializer circuit is further configured to reset the first counter in response to a determination that the given time period has expired, and reset the first counter in response to a determination that the first training operation has completed. 
     
     
       5. The apparatus of  claim 3 , wherein the deserializer circuit is further configured to determine the number of first training operations performed during the particular period of time, and increment a second counter in response to a determination that the first training operation has completed. 
     
     
       6. The apparatus of  claim 5 , wherein the deserializer circuit is further configured to reset the second counter in response to a determination that the particular period of time has expired, and reset the second counter in response to a determination that the second training operation has completed. 
     
     
       7. A method, comprising:
 transmitting, by a serializer circuit, a data stream including multiple data words via a communication channel, wherein a particular data word includes a plurality of data bits and a header; 
 receiving, by a deserializer circuit, the data stream via a communication channel; 
 determining, by the deserializer circuit, a number of errors during reception of a given data word of the multiple data words; 
 in response to detecting, by the deserializer circuit, an end of the given data word:
 initiating a first training operation to adjust a sampling point, in response to determining that the number of errors is greater than a threshold number of errors; and 
 initiating a second training operation to adjust the sampling point, in response to determining that a number of first training operations previously performed during a particular period of time is greater than a threshold number of previously performed first training operations, 
 
 in response to initiating the first training operation, transmitting, by the serializer circuit, a first number of training data bits; and 
 in response to initiating the first training operation, transmitting, by the deserializer circuit, a second number of training data bits, wherein the second number of training data bits is greater than the first number of training data bits. 
 
     
     
       8. The method of  claim 7 , wherein determining the number of errors during the reception of the plurality of data bits comprises performing a Cyclic Redundancy Check (CRC). 
     
     
       9. The method of  claim 7 , wherein determining the number of errors during the reception of the plurality of data bits comprises incrementing a first counter in response to detecting an error in the given data word in a given time period. 
     
     
       10. The method of  claim 9 , further comprising resetting the first counter in response to determining the given time period has expired, and wherein performing the first training operation comprises resetting the first counter. 
     
     
       11. The method of  claim 9 , wherein determining that the number of first training operations performed during the particular period of time comprises incrementing a second counter in response to determining the first training operation has completed. 
     
     
       12. The method of  claim 11 , further comprising resetting the second counter in response to determining particular period of time has expired, and wherein performing the second training operation comprises resetting the second counter. 
     
     
       13. The method of  claim 7 , wherein performing the second training operation comprises performing one or more software instructions by a processing unit. 
     
     
       14. A system, comprising:
 a first communication transceiver unit including a serializer circuit configured to convert parallel data into a serial data stream including multiple data words and transmit the serial data stream via a communication channel, wherein a particular data word includes a plurality of data bits and a header; and 
 a second communication transceiver unit, including a deserializer circuit configured to:
 receive the receive the serial data stream via the communication channel; 
 determine a number of errors during reception of a given data word of the multiple data words; 
 in response to a detection of an end of the given data word:
 initiate a first training operation to adjust a sampling point, in response to a determination that the number of errors is greater than a threshold number of errors; and 
 initiate a second training operation to adjust the sampling point, in response to a determination that a number of first training operations previously performed during a particular period of time is greater than a threshold number of previously performed first training operations; and 
 
 
 wherein the serializer circuit is further configured to configured to transmit a first number of training data bits during the first training operation and transmit a second number of training data bits during the second training operation, wherein the second number of training data bits is greater than the first number of training data bits. 
 
     
     
       15. The system of  claim 14 , wherein to determine the number of errors in the data, the deserializer circuit is further configured to perform a Cyclic Redundancy Check (CRC). 
     
     
       16. The system of  claim 14 , wherein to determine the number of errors during the reception of the plurality of data bits, the deserializer circuit is further configured to increment a first counter in response to detecting an error in the given data word in a given time period of a plurality of time periods. 
     
     
       17. The system of  claim 16 , wherein the deserializer circuit is further configured to reset the first counter in response to a determination that a given time period has expired, and wherein to perform the first training operation, the deserializer circuit is further configured to reset the first counter in response to a determination that the first training operation has completed. 
     
     
       18. The system of  claim 16 , wherein to determine that the number of first training operations performed during the particular period of time, the deserializer circuit is further configured to increment a second counter in response to a determination that the first training operation has completed. 
     
     
       19. The system of  claim 18 , wherein the deserializer circuit is further configured to reset the second counter in response to a determination that a given time period of a plurality of time periods has expired, and wherein to perform the second training operation, the deserializer circuit is further configured to reset the second counter in response to a determination that the second training operation has completed. 
     
     
       20. The system of  claim 14 , wherein performing the second training operation, the deserializer circuit is further configured to perform one or more software instructions by a processing unit.