Using inter-tier vias in integrated circuits

Abstract

Various implementations described herein may be directed to using inter-tier vias (IVs) in integrated circuits (ICs). In one implementation, a three-dimensional (3D) IC may include a plurality of tiers disposed on a substrate layer, where the tiers may include a first tier having a first active device layer electrically coupled to first interconnect layers, and may also include a second tier having a second active device layer electrically coupled to a second interconnect layer, where the first interconnect layers include an uppermost layer that is least proximate to the first active device layer. The 3D IC may further include IVs to electrically couple the second interconnect layer and the uppermost layer. The uppermost layer may be electrically coupled to a power source at peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer.

What is claimed is: 
     
       1. A three-dimensional (3D) integrated circuit (IC), comprising:
 a plurality of tiers disposed on a substrate layer, wherein the plurality of tiers comprises:
 a first tier having a first active device layer electrically coupled to one or more first interconnect layers; 
 a second tier having a second active device layer electrically coupled to a second interconnect layer, wherein the first tier is positioned closer to the substrate layer than the second tier, and wherein the one or more first interconnect layers include an uppermost first interconnect layer that is least proximate to the first active device layer of the first interconnect layers; 
 
 one or more first inter-tier vias (IVs) configured to couple to the second interconnect layer and to the uppermost first interconnect layer; and 
 wherein the uppermost first interconnect layer is coupled to one or more peripheral input structures at one or more peripheral locations of the first tier, wherein the one or more peripheral input structures are configured to electrically couple the uppermost first interconnect layer to a power source, thereby electrically coupling the power source to the first active device layer and to the second active device layer. 
 
     
     
       2. The 3D IC of  claim 1 , wherein respective peripheral input structures comprise:
 a contact electrically coupled to the uppermost first interconnect layer; and 
 a wire-bond input electrically coupled to the contact and configured to receive power from the power source. 
 
     
     
       3. The 3D IC of  claim 2 , wherein the first tier is larger in size than the second tier, and wherein the one or more peripheral locations are positioned to be adjacent to a side of the second tier. 
     
     
       4. The 3D IC of  claim 1 , wherein the one or more peripheral locations of the first tier comprise one or more locations that are proximate to an edge of the first tier. 
     
     
       5. The 3D IC of  claim 1 , wherein the uppermost first interconnect layer is configured to provide power to the first active device layer through the one or more first interconnect layers, and wherein the uppermost first interconnect layer is configured to provide power to the second active device layer through the one or more first IVs and the second interconnect layer. 
     
     
       6. The 3D IC of  claim 1 , wherein the first tier and the second tier are positioned approximately in the middle of the plurality of tiers. 
     
     
       7. The 3D IC of  claim 1 , wherein the 3D IC is a monolithic 3D IC, and wherein the first IVs comprise one or more monolithic inter-tier vias (MIVs). 
     
     
       8. The 3D IC of  claim 1 , wherein the one or more first interconnect layers and the second interconnect layer are composed of metal. 
     
     
       9. The 3D IC of  claim 1 , further comprising one or more input structures positioned proximate to a center of the 3D IC and positioned at least partially on a top side of the second tier, wherein the one or more input structures are configured to electrically couple the power source to the first active device layer and to the second active device layer using a plurality of metal layers and one or more second IVs. 
     
     
       10. The 3D IC of  claim 9 , wherein the one or more input structures comprise one or more solder bumps electrically coupled to the plurality of metal layers and the one or more second IVs. 
     
     
       11. The 3D IC of  claim 1 , wherein respective peripheral input structures comprise:
 a through silicon via (TSV) electrically coupled to the uppermost first interconnect layer; and 
 a solder bump disposed at a top side of the second tier, electrically coupled to the TSV, and configured to receive power from the power source. 
 
     
     
       12. A three-dimensional (3D) integrated circuit (IC), comprising:
 a plurality of tiers disposed on a substrate layer, wherein the plurality of tiers comprises:
 a first tier having a first active device layer electrically coupled to one or more first interconnect layers; 
 a second tier having a second active device layer electrically coupled to a second interconnect layer, wherein the first tier is positioned closer to the substrate layer than the second tier, and wherein the one or more first interconnect layers include an uppermost first interconnect layer that is least proximate to the first active device layer of the first interconnect layers; 
 
 one or more first inter-tier vias (IVs) configured to electrically couple the second interconnect layer and the uppermost first interconnect layer; 
 wherein the uppermost first interconnect layer is electrically coupled to a power source at one or more peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer; 
 wherein the uppermost first interconnect layer is electrically coupled to the power source at the one or more peripheral locations of the first tier using one or more peripheral input structures, wherein respective peripheral input structures comprise:
 a first through silicon via (TSV) electrically coupled to the uppermost first interconnect layer; and 
 a first solder bump disposed at a top side of the second tier, electrically coupled to the TSV, and configured to receive power from the power source; and 
 
 further comprising one or more central input structures positioned proximate to a center of the 3D IC and coupled to the power source, wherein the one or more central input structures comprise:
 a second through silicon via (TSV) electrically coupled to the uppermost first interconnect layer; and 
 a second solder bump disposed at the top side of the second tier, electrically coupled to the TSV, and configured to receive power from the power source. 
 
 
     
     
       13. A three-dimensional (3D) integrated circuit (IC), comprising:
 a plurality of tiers disposed on a substrate layer, wherein the plurality of tiers comprises:
 a first tier having a first active device layer electrically coupled to one or more first interconnect layers; 
 a second tier having a second active device layer electrically coupled to a second interconnect layer, wherein the first tier is positioned closer to the substrate layer than the second tier, and wherein the one or more first interconnect layers include an uppermost first interconnect layer that is least proximate to the first active device layer of the first interconnect layers; 
 
 one or more first inter-tier vias (IVs) configured to electrically couple the second interconnect layer and the uppermost first interconnect layer; 
 wherein the uppermost first interconnect layer is electrically coupled to a power source at one or more peripheral locations of the first tier, thereby electrically coupling the power source to the first active device layer and to the second active device layer; 
 wherein the uppermost first interconnect layer is electrically coupled to the power source at the one or more peripheral locations of the first tier using one or more peripheral input structures, wherein respective peripheral input structures comprise:
 a through silicon via (TSV) electrically coupled to the uppermost first interconnect layer; and 
 a solder bump disposed at a top side of the second tier, electrically coupled to the TSV, and configured to receive power from the power source; and 
 
 wherein the uppermost first interconnect layer is electrically coupled to an adjacent first interconnect layer, wherein:
 the adjacent first interconnect layer is larger in pitch than the uppermost first interconnect layer; and 
 the adjacent first interconnect layer is electrically coupled to the TSV, thereby electrically coupling the TSV to the uppermost first interconnect layer. 
 
 
     
     
       14. A three-dimensional (3D) integrated circuit (IC), comprising:
 a plurality of tiers disposed on a substrate layer, wherein the plurality of tiers comprises:
 a first tier having a first active device layer electrically coupled to one or more first interconnect layers; 
 a second tier having a second active device layer electrically coupled to one or more second interconnect layers, wherein the first tier is positioned closer to the substrate layer than the second tier, and wherein the one or more first interconnect layers include an uppermost first interconnect layer that is least proximate to the first active device layer of the first interconnect layers; 
 
 one or more first inter-tier vias (IVs) configured to couple to one of the one or more second interconnect layers and to the uppermost first interconnect layer; and 
 wherein the uppermost first interconnect layer is coupled to one or more peripheral input structures at one or more peripheral locations of the first tier, wherein the one or more peripheral input structures are configured to electrically couple the uppermost first interconnect layer to a clock source, an input signal source, or combinations thereof, thereby electrically coupling the clock source, the input signal source, or combinations thereof to the first active device layer and to the second active device layer. 
 
     
     
       15. The 3D IC of  claim 14 , wherein respective peripheral input structures comprise:
 a contact electrically coupled to the uppermost first interconnect layer; and 
 a wire-bond input electrically coupled to the contact and configured to receive one or more signals from the clock source, the input signal source, or combinations thereof. 
 
     
     
       16. The 3D IC of  claim 14 , wherein the one or more peripheral locations of the first tier comprise one or more locations that are proximate to an edge of the first tier. 
     
     
       17. The 3D IC of  claim 14 , wherein the uppermost first interconnect layer is configured to provide one or more signals from the clock source, the input signal source, or combinations thereof to the first active device layer through the one or more first interconnect layers, and wherein the uppermost first interconnect layer is configured to provide the one or more signals from the clock source, the input signal source, or combinations thereof to the second active device layer through the one or more first IVs and the one or more second interconnect layers. 
     
     
       18. An integrated circuit, comprising:
 an active device layer disposed on a substrate layer; 
 one or more first interconnect layers disposed on a top side of the active device layer and electrically coupled to the active device layer, wherein the one or more first interconnect layers include a bottommost first interconnect layer that is most proximate to the active device layer of the first interconnect layers; 
 one or more second interconnect layers disposed on a bottom side of the active device layer, wherein the one or more second interconnect layers include an uppermost second interconnect layer that is most proximate to the active device layer of the second interconnect layers; 
 one or more first inter-tier vias (IVs) configured to couple to the bottommost first interconnect layer and to the uppermost second interconnect layer; and 
 wherein the one or more second interconnect layers is electrically coupled to a power source, a clock source, an input signal source, or combinations thereof, thereby electrically coupling the power source, the clock source, the input signal source, or combinations thereof to the active device layer. 
 
     
     
       19. The integrated circuit of  claim 18 , wherein the uppermost second interconnect layer is electrically coupled to the power source, the clock source, the input signal source, or combinations thereof at one or more peripheral locations of the integrated circuit. 
     
     
       20. The integrated circuit of  claim 18 , further comprising a solder bump disposed on the bottom side of the active device layer, wherein the solder bump is electrically coupled to the power source, the clock source, the input signal source, or combinations thereof, and wherein the one or more second interconnect layers is electrically coupled to the solder bump.