Operational amplifier circuit

Abstract

In an output amplifier stage of an operational amplifier circuit, the first p-well of the first nMOSFET and the second p-well of the second nMOSFET are connected to the fourth node. Further, the first n-well of the first pMOSFET and the second n-well of the second pMOSFET are connected to the fifth node. At least one of the fourth node and the fifth node is connected to an output terminal VOUT.

The invention claimed is: 
     
       1. An operational amplifier circuit comprising an output amplifier stage that amplifies a first voltage of a differential amplifier stage outputting the first voltage, and that outputs a voltage that is amplified from an output terminal, wherein the output amplifier stage includes:
 a first nMOSFET in which a first p-well is formed, a gate and a drain which are short-circuited are connected to a first node, and a source is connected to a second node; 
 a second nMOSFET in which a second p-well is formed, a gate is connected to the first node, a drain is connected to a first reference terminal, and a source is connected to the output terminal; 
 a first pMOSFET in which a first n-well is formed, a gate and a drain which are short-circuited are connected to a third node, and a source is connected to the second node; and 
 a second pMOSFET in which a second n-well is formed, a gate is connected to the third node, a drain is connected to a second reference terminal, and a source is connected to the output terminal, 
 and wherein the first p-well and the second p-well are connected to a fourth node, 
 the first n-well and the second n-well are connected to a fifth node, 
 and at least one of the fourth node and the fifth node is connected to the output terminal. 
 
     
     
       2. The operational amplifier circuit as defined in  claim 1 , wherein the output amplifier stage further includes:
 a third pMOSFET in which a gate is connected to a sixth node, a drain is connected to the first node, and a source is connected to the first reference terminal; and 
 a third nMOSFET in which a gate is connected to a seventh node, a drain is connected to the third node, and a source is connected to the second reference terminal, 
 and wherein the first voltage is supplied to one of the sixth node and the seventh node, 
 and a bias voltage is supplied to the other of the sixth node and the seventh node. 
 
     
     
       3. The operational amplifier circuit as defined in  claim 1 , wherein the first n-well and the second n-well are separated from each other, and are connected to the fifth node by a wiring layer. 
     
     
       4. The operational amplifier circuit as defined in  claim 1 , wherein the first n-well and the second n-well are formed as a single region by a single n-well, and are connected to the fifth node by a wiring layer. 
     
     
       5. The operational amplifier circuit as defined in  claim 1 , wherein the first p-well and the second p-well are separated from each other by a third n-well, and are connected to the fourth node by a wiring layer. 
     
     
       6. The operational amplifier circuit as defined in  claim 1 , wherein the first p-well and the second p-well are formed as a single region by a single p-well, and are connected to the fourth node by a wiring layer. 
     
     
       7. The operational amplifier circuit as defined in  claim 1 , wherein the differential amplifier stage has a differential pair including two nMOSFETs. 
     
     
       8. The operational amplifier circuit as defined in  claim 1 , wherein the differential amplifier stage has a differential pair including two pMOSFETs.