Method, system and device for non-volatile memory device state detection

Abstract

Disclosed are methods, systems and devices for operation of non-volatile memory devices. In one aspect, a sense circuit may enable a determination of a current impedance state of a non-volatile memory element while avoiding an unintentional change in the state of the non-volatile memory element.

What is claimed is: 
     
       1. A device comprising:
 one or more non-volatile memory elements, at least one of the one or more non-volatile memory elements comprising a first terminal coupled to a bitline and a second terminal coupled to a node; 
 a sense voltage source coupled to the first terminal through a load; and 
 a circuit coupled to the first terminal through the bitline to detect an impedance state of the at least one of the one or more non-volatile memory elements as either a low impedance or conductive state, or a high impedance or insulative state based, at least in part, on a signal on the bitline, 
 wherein the load comprises an impedance that is at least as large as an impedance between the first and second terminals of the at least one of the one or more non-volatile memory elements while the at least one of the one or more non-volatile memory elements is in the low impedance or conductive state. 
 
     
     
       2. The device of  claim 1 , wherein the second terminal is coupled to the node through a conducting element that is configured to connect the second terminal to the node responsive to a signal on a wordline. 
     
     
       3. The device of  claim 1 , wherein the load comprises one or more devices formed from correlated electron material. 
     
     
       4. The device of  claim 1 , wherein the load comprises one or more correlated electron switches (CESs) connected in series. 
     
     
       5. The device of  claim 1 , wherein the load comprises at least a load across source and drain terminals of a field effect transistor. 
     
     
       6. The device of  claim 4 , wherein the one or more CESs are maintained in a conductive or low impedance state. 
     
     
       7. The device of  claim 1 , wherein the at least one of the one or more nonvolatile memory elements is capable of being placed in a high impedance or insulative state, or a low impedance or conductive state. 
     
     
       8. The device of  claim 7 , wherein the load comprises a resistance that is greater than a resistance of the at least one of the one or more non-volatile memory elements. 
     
     
       9. The device of  claim 1 , wherein the circuit coupled to the first terminal through the bitline is configured to detect the impedance state based, at least in part, on a voltage of the bitline. 
     
     
       10. The device of  claim 9 , and further comprising a conducting element to selectively couple the bitline to the node based, at least in part, on the impedance state. 
     
     
       11. A method comprising:
 coupling a first terminal of a non-volatile memory element to a node on a bitline, the node on the bitline being coupled to a voltage source through a load, a second terminal of the non-volatile memory element being coupled to a reference node; and 
 detecting an impedance state of the non-volatile memory element as either a low impedance or conductive state, or a high impedance or insulative state based, at least in part, on a voltage at the node on the bitline, 
 wherein the load comprises an impedance that is at least as large as an impedance between the first and second terminals of the non-volatile memory element while the non-volatile memory element is in the low impedance or conductive state. 
 
     
     
       12. The method of  claim 11 , wherein the non-volatile memory element is selected from a plurality of non-volatile memory elements at least in part in response to a voltage on a wordline. 
     
     
       13. The device of  claim 1 , wherein the load comprises one or more devices formed from material substantially the same as material formed between the first and second terminals of the at least one of the one or more non-volatile memory elements. 
     
     
       14. The device of  claim 1 , wherein the at least one of the one or more non-volatile memory elements comprises a correlated electron switch (CES) comprising a correlated electron material (CEM) formed between the first and second terminals of the at least one of the one or more non-volatile memory elements, and wherein the load comprises one or more devices comprising the CEM formed between the sense voltage source and the bitline.