Semiconductor device including channel structure

Abstract

A semiconductor device includes a stacked structure disposed on a semiconductor substrate. The stacked structure includes interlayer insulating layers and gate electrodes, alternately stacked. Separation patterns are disposed to penetrate the stacked structure. A channel structure is disposed between the separation patterns. The channel structure includes a horizontal portion interposed between the stacked structure and the semiconductor substrate while being in contact with the semiconductor substrate and includes vertical portions extending from the horizontal portion in a vertical direction and penetrating the stacked structure. A lower structure is interposed between the horizontal portion and the separation patterns. A dielectric structure is interposed between the vertical portions and the stacked structure and extends between the horizontal portion and the stacked structure.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a stacked structure disposed on a semiconductor substrate, the stacked structure including interlayer insulating layers and gate electrodes, alternately stacked; 
 separation patterns disposed on the semiconductor substrate and penetrating through the stacked structure; 
 a channel structure disposed between two of the separation patterns, the channel structure including a horizontal portion interposed between the stacked structure and the semiconductor substrate while being in contact with the semiconductor substrate and including a plurality of vertical portions extending from the horizontal portion in a vertical direction and penetrating through the stacked structure; 
 a lower structure interposed between the horizontal portion and the separation patterns; and 
 a dielectric structure interposed between the plurality of vertical portions and the stacked structure and extending between the horizontal portion and the stacked structure. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein a lower surface of the lower structure is coplanar with a lower surface of the horizontal portion. 
     
     
       3. The semiconductor device of  claim 1 , wherein the lower structure comprises a first lower pattern and a second lower pattern disposed on the first lower pattern. 
     
     
       4. The semiconductor device of  claim 3 , wherein the second lower pattern is thicker than the first lower pattern. 
     
     
       5. The semiconductor device of  claim 3 , wherein the first lower pattern is formed of an insulating material, and the second lower pattern is formed of polysilicon. 
     
     
       6. The semiconductor device of  claim 3 , wherein the first lower pattern is in contact with the horizontal portion, the second lower pattern is disposed to be spaced apart from the horizontal portion, and the dielectric structure extends between the horizontal portion and the second lower pattern. 
     
     
       7. The semiconductor device of  claim 3 , wherein the first lower pattern and the second lower pattern are in contact with the horizontal portion. 
     
     
       8. The semiconductor device of  claim 1 , further comprising insulating spacers on side surfaces of the separation patterns,
 wherein the separation patterns are spaced apart from the gate electrodes by the insulating spacers. 
 
     
     
       9. The semiconductor device of  claim 1 , further comprising impurity regions disposed in the semiconductor substrate and adjacent to the separation patterns. 
     
     
       10. The semiconductor device of  claim 9 , wherein the lower structure comprises a first lower pattern and a second lower pattern disposed on the first lower pattern, and the first lower pattern is formed of polysilicon having a conductivity type the same as a conductivity type of the impurity regions. 
     
     
       11. A semiconductor device, comprising:
 a plurality of gate electrodes disposed on a semiconductor substrate; 
 a channel structure including a horizontal portion in contact with the semiconductor substrate and disposed below the plurality of gate electrodes and including a plurality of vertical portions extending from the horizontal portion in a vertical direction and penetrating through the plurality of gate electrodes; 
 a dielectric structure covering an upper surface of the horizontal portion, extending on side surfaces of the plurality of vertical portions, and interposed between the plurality of vertical portions and the plurality of gate electrodes; and 
 a lower structure interposed between the plurality of gate electrodes and the semiconductor substrate, 
 wherein a lower surface of the lower structure is coplanar with a lower surface of the horizontal portion. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the lower structure comprises a first lower pattern and a second lower pattern disposed on the first lower pattern while being thicker than the first lower pattern, and the second lower pattern is formed of polysilicon. 
     
     
       13. The semiconductor device of  claim 11 , further comprising separation patterns penetrating through the plurality of gate electrodes and extending to an interior of the semiconductor substrate; and impurity regions disposed in the semiconductor substrate and adjacent to the separation patterns,
 wherein the lower structure is interposed between the separation patterns and the horizontal portion. 
 
     
     
       14. The semiconductor device of  claim 13 , wherein the lower structure comprises a lower pattern formed of polysilicon having a conductivity type the same as a conductivity type of the impurity regions. 
     
     
       15. The semiconductor device of  claim 11 , wherein the lower structure has a side surface facing the horizontal portion, and at least a portion of the side surface of the lower structure is in contact with the horizontal portion. 
     
     
       16. A semiconductor device, comprising:
 a stacked structure disposed to be spaced apart from a semiconductor substrate, the stacked structure including interlayer insulating layers and gate electrodes, alternately stacked; 
 separation patterns disposed on the semiconductor substrate and penetrating through the stacked structure; 
 impurity regions disposed in the semiconductor substrate and adjacent to the separation patterns; 
 a channel structure disposed between two of the separation patterns, the channel structure including a horizontal portion in contact with the semiconductor substrate and a plurality of vertical portions extending from the horizontal portion in a vertical direction and penetrating through the stacked structure; and 
 a lower structure interposed between the horizontal portion and the separation patterns. 
 
     
     
       17. The semiconductor device of  claim 16 , further comprising a dielectric structure interposed between the channel structure and the stacked structure,
 wherein the dielectric structure includes a charge trapping layer. 
 
     
     
       18. The semiconductor device of  claim 16 , wherein the lower structure comprises a polysilicon layer having a conductivity type the same as a conductivity type of the impurity regions. 
     
     
       19. The semiconductor device of  claim 16 , wherein a lower surface of the lower structure is coplanar with a lower surface of the horizontal portion. 
     
     
       20. The semiconductor device of  claim 16 , further comprising pad patterns in contact with upper regions of the plurality of vertical portions; and core patterns interposed between the pad patterns and the horizontal portion and surrounded by the plurality of vertical portions.