Wide bandwidth, high resolution circuitry for phase shifted frequency detection

Abstract

Phase shifted frequency components of wide bandwidth, composite signals areocused for analysis with high resolution by circuitry which includes both a Chirp-Z and a superheterodyne signal analyzer. An interface between the analyzers synchronizes the outputs therefrom relative to each phase shifted frequency component. Preferred embodiments are disclosed with the analyzers generally arranged in either parallel or series and replicating circuitry may be included in the latter to sustain the integrity of the phase shifted frequency components for some predetermined period of time.

What I claim is: 
     
       1. Circuitry for analyzing the phase shifted frequency components of composite signals, comprising: a wide bandwidth Chirp-Z signal analyzer for deriving segregated time domain outputs of the phase shifted frequency components;   a swept-tuned, narrow bandwidth superheterodyne signal analyzer for outputting the phase shifted frequency components with high resolution; and   interface means between said Chirp-Z and superheterodyne analyzers for sychronizing the presence of the phase shifted frequency components at the outputs of those analyzers.   
     
     
       2. The circuitry of claim 1 wherein said interface means includes a voltage controlled oscillator having its output applied to rough tune said superheterodyne analyzer. 
     
     
       3. The circuitry of claim 2 wherein said interface means further includes means for controlling the voltage input to said voltage controlled oscillator in accordance with the relative position occupied by the phase shifted frequency components in the frequency seqregated time domain output of said Chirp-Z analyzer. 
     
     
       4. The circuitry of claim 3 wherein said voltaqe control means further includes; a video detector having the phase shifted frequency components in the frequency segregated time domain output of said Chirp-Z analyzer applied thereto and deriving unique pulse counts therefrom for each phase shifted frequency component represented in said Chirp-Z analyzer output;   a frequency/time counter and logic control unit having the unique pulse counts from said video detector applied thereto and deriving information therefrom to identify each phase shifted frequency component in accordance with the relative position occupied thereby in the frequency segregated time domain of said Chirp-Z analyzer;   a frequency word generator having the identifying information from said frequency/time counter and logic control unit applied thereto and deriving a digital code therefrom for each phase shifted frequency component;   a memory and microprocessor unit having the digital codes from said frequency word generator applied thereto and deriving a digital representation therefrom for a voltage in accordance with the frequency difference between the selected frequency component and the frequency output of said voltage controlled oscillator; and   a digital-to-analog converter having the digital representation from said memory and microprocessor unit applied thereto and directing the equivalent analog voltage therefor to said voltage controlled oscillator.   
     
     
       5. The circuitry of claim 1 wherein said Chirp-Z and superheterodyne analyzers are arranged in parallel. 
     
     
       6. The circuitry of claim 5 wherein said interface means includes a voltage controlled oscillator having its output applied to a mixer within said superheterodyne analyzer for tuning that analyzer. 
     
     
       7. The circuitry of claim 6 wherein the superheterodyne analyzer output passes from a filter, delay and combining circuit and the voltage of said oscillator is controlled in accordance with the frequency difference between the individual phase shifted frequency components and the center frequency of that circuit. 
     
     
       8. The circuitry of claim 1 wherein said Chirp-Z and superheterodyne analyzers are arranged in series. 
     
     
       9. The circuitry of claim 8 wherein said interface means includes a voltage controlled oscillator having its output applied to a mixer within said superheterodyne analyzer for tuning that analyzer. 
     
     
       10. The circuitry of claim 9 wherein the superheterodyne analyzer output passes from a filter, delay and combining circuit and the voltage of said oscillator is controlled in accordance with the frequency difference between the individual phase shifted frequency components and the center frequency of that circuit. 
     
     
       11. The circuitry of claim 8 wherein output from said Chirp-Z analyzer is directed to the input of said superheterodyne analyzer through a means for replicating the phase shifted frequency components to sustain the integrity thereof over some predetermined period of time. 
     
     
       12. The circuitry of claim 11 wherein said replicating means directs output from said Chirp-Z analyzer to the input of said superheterodyne analyzer through a tapped delay line having feedback from its output through a switch to its input, while said switch is controlled through a fixed delay line with output from said Chirp-Z analyzer. 
     
     
       13. Circuitry for analyzing the phase shifted frequency components of composite signals, comprising: a single antenna for receiving the composite signals;   a swept-tuned, narrow bandwidth superheterodyne signal analyzer for outputting the phase shifted frequency components with high resolution;   a wide bandwidth Chirp-Z signal analyzer for deriving segregated time domain outputs of the phase shifted frequency components, said Chirp-Z signal analyzer being series connected between said antenna and said superheterodyne analyzer; and   interface means between said Chirp-Z and superheterodyne analyzers for synchronizing the presence of the phase shifted frequency components at the outputs of those analyzers.   
     
     
       14. The circuitry of claim 13 wherein said interface means includes a voltage controlled oscillator having its output applied to rough tune said superheterodyne analyzer. 
     
     
       15. The circuitry of claim 14 wherein said interface means further includes means for controlling the voltage input to said voltage controlled oscillator in accordance with the relative position occupied by the phase shifted frequency components in the frequency segregated time domain output of said Chirp-Z analyzer. 
     
     
       16. The circuitry of claim 15 wherein said voltage control means further includes; a video detector having the phase shifted frequency components in the frequency segregated time domain output of said Chirp-Z analyzer applied thereto and deriving unique pulse counts therefrom for each phase shifted frequency component represented in said Chirp-Z analyzer output;   a frequency/time counter and logic control unit having the unique pulse counts from said video detector applied thereto and deriving information therefrom to identify each phase shifted frequency component in accordance with the relative position occupied thereby in the frequency segregated time domain of said Chirp-Z analyzer;   a frequency word generator having the identifying information from said frequency/time counter and logic control unit applied thereto and deriving a digital code therefrom for each phase shifted frequency component;   a memory and microprocessor unit having the digital codes from said frequency word generator applied thereto and deriving a digital representation therefrom for a voltage in accordance with the frequency difference between the selected frequency component and the frequency output of said voltage controlled oscillator; and   a digital-to-analog converter having the digital representation from said memory and microprocessor unit applied thereto and directing the equivalent analog voltage therefor to said voltage controlled oscillator.   
     
     
       17. The circuitry of claim 13 wherein said interface means includes a voltage controlled oscillator having its output applied to a mixer within said superheterodyne analyzer for tuning that analyzer. 
     
     
       18. The circuitry of claim 17 wherein said superheterodyne analyzer output passes from a filter, delay and combining circuit and the voltage of said oscillator is controlled in accordance with the frequency difference between the individual phase shifted frequency components and the center frequency of that circuit. 
     
     
       19. The circuitry of claim 13 wherein output from said Chirp-Z analyzer is directed to the output of said superheterodyne analyzer through a means for replicating the phase shfted frequency components to sustain the integrity thereof over some predetermined period of time. 
     
     
       20. The circuitry of claim 19 wherein said replicating means direct output from said Chirp-Z analyzer to the input of said superheterodyne analyzer through a tapped delay line having feedback from its output through a switch to its input, while said switch is controlled through a fixed delay line with output from said Chirp-Z analyzer.