Method and circuit for eliminating hold time violations in synchronous circuits

Abstract

Circuits and methods for eliminating hold time violations are disclosed. A DE-type flip-flop latches a data input signal on a data input terminal a fraction of a clock period before a triggering edge of the clock signal. The DE-type flip-flop provides a data output signal for a full clock period beginning after the triggering edge of the clock signal. The DE-type flip-flop includes a latch having its data output terminal coupled to the data input terminal of a flip-flop. The flip-flop clock input pin and the latch enable terminal of the latch are connected to a clock line. The DE-type flip-flop used in place of a standard flip-flop, in which a hold time violation occurs, eliminates the hold time violation.

We claim: 
     
       1. A DE-type flip-flop comprising a data input terminal;   a first clock input terminal wherein a first clock input signal on said first clock input terminal has a plurality of active edges, a plurality of nonactive edges, and a first clock input signal clock period; and   a data output terminal coupled to said data input terminal in response to a first active edge of said first clock input signal; wherein a data input signal on said data input terminal is sampled a predetermined fraction of said first clock input signal clock period before a first active edge of said first clock input signal; said data input signal is applied on said data output terminal in response to said first active edge; and said data input signal is maintained on said data output terminal for said first clock input signal clock period.     
     
     
       2. The DE-type flip-flop of claim 1, wherein said first active edge is a rising edge. 
     
     
       3. The DE-type flip-flop of claim 1, wherein said predetermined fraction is one-fourth. 
     
     
       4. The DE-type flip-flop of claim 1, wherein said predetermined fraction is one-half. 
     
     
       5. The DE-type flip-flop of claim 1, further comprising: a latch having a latch data input terminal coupled to said data input terminal, a latch data output terminal, and a latch enable input terminal coupled to said first clock input terminal; and   a flip-flop having a flip-flop data input terminal coupled to said latch data output terminal, a flip-flop data output terminal coupled to said data output terminal, and a flip-flop clock input terminal coupled to said first clock input terminal.   
     
     
       6. The DE-type flip-flop of claim 1, further comprising: a second clock input terminal wherein a second clock input signal on said second clock input terminal has a second clock input signal clock period;   a latch having a latch data input terminal coupled to said data input terminal, a latch data output terminal, and a latch enable input terminal coupled to said first clock input terminal; and   a flip-flop having a flip-flop data input terminal coupled to said latch data output terminal, a flip-flop data output terminal coupled to said data output terminal, and a flip-flop clock input terminal coupled to said second clock input terminal.   
     
     
       7. The DE-type flip-flop of claim 6, wherein said second clock input signal clock period is half of said first clock input signal clock period. 
     
     
       8. The DE-type flip-flop of claim 5, wherein said flip-flop is a master-slave D-type flip-flop. 
     
     
       9. The DE-type flip-flop of claim 5, wherein said latch further comprises a transmission gate having a transmission gate data input terminal coupled to said data input terminal, a first transmission gate control input terminal coupled to said first clock input terminal, a second transmission gate control input terminal coupled to a second clock input terminal, wherein said second clock input terminal receives an inverted version of said first clock input signal, and a transmission gate data output terminal;   a first inverter having a first inverter input terminal coupled to said transmission gate data output terminal and a first inverter output terminal; and   a second inverter having a second inverter input terminal coupled to said first inverter output terminal and a second inverter output terminal coupled to both said first inverter input terminal and said data input terminal.   
     
     
       10. An DE-type flip-flop as in claim 1, wherein said data input terminal of said DE-type flip-flop is coupled to a second flip-flop data output terminal of a second flip-flop; and said first clock input terminal of said DE-type flip-flop is coupled to a flip-flop clock input terminal of said second flip-flop. 
     
     
       11. The DE-type flip-flop of claim 10, wherein said DE-type flip-flop and said second flip-flop are on a single integrated circuit. 
     
     
       12. The DE-type flip-flop of claim 10, wherein said DE-type flip-flop is on a first integrated circuit and said second flip-flop is on a second integrated circuit. 
     
     
       13. The DE-type flip-flop of claim 10, wherein said DE-type flip-flop and said second flip-flop are on a single circuit board. 
     
     
       14. The DE-type flip-flop of claim 10, wherein said DE-type flip-flop is on a first circuit board and said second flip-flop is on a second circuit board. 
     
     
       15. The DE-type flip-flop of claim 10, wherein said second flip-flop data output terminal of said second flip-flop is coupled to said data input terminal of said DE-type flip-flop through at least one intermediate gate. 
     
     
       16. A DE-type flip-flop comprising a latch having a latch data input terminal, a latch data output terminal, and a latch enable input terminal;   a flip-flop having a flip-flop data input terminal connected directly to said latch data output terminal, a flip-flop data output terminal, and a flip-flop clock input terminal;   a DE data input terminal connected directly to said latch data input terminal;   a first DE clock input terminal coupled to said flip-flop clock input terminal;   a second DE clock input terminal coupled to said latch enable input terminal; and   a DE data output terminal connected directly to said flip-flop data output terminal wherein a data input signal on said DE data input terminal is stored in said latch a predetermined fraction of a clock period of a clock input signal before a first active edge of said clock input signal on said first DE clock input terminal; said data input signal is applied on said DE data output terminal in response to said first active edge; and said data input signal is maintained on said DE data output terminal for said clock period of said clock input signal.     
     
     
       17. The DE-type flip-flop of claim 16, wherein said first DE clock input terminal is coupled to said second DE clock input terminal. 
     
     
       18. The DE-type flip-flop of claim 16, wherein said flip-flop is a master-slave D-type flip-flop. 
     
     
       19. The DE-type flip-flop of claim 16, wherein said latch further comprises a transmission gate having a transmission gate data input terminal coupled to said DE data input terminal, a first transmission gate control input terminal coupled to said first DE clock input terminal, a second transmission gate control input terminal; and a transmission gate data output terminal;   a first inverter having a first inverter input terminal coupled to said transmission gate data output terminal and a first inverter output terminal;   a second inverter having a second inverter input terminal coupled to said first inverter output terminal and a second inverter output terminal coupled to both said first inverter input terminal and said DE data input terminal; and   a third DE clock input terminal coupled to said second transmission gate control input terminal.   
     
     
       20. An DE-type flip-flop as in claim 16, wherein said DE data input terminal is coupled to a second flip-flop data output terminal of a second flip-flop; and said first DE clock input terminal is coupled to a flip-flop clock input terminal of said second flip-flop. 
     
     
       21. The DE-type flip-flop of claim 20, wherein said DE-type flip-flop and said second flip-flop are on a single integrated circuit. 
     
     
       22. The DE-type flip-flop of claim 20, wherein said DE-type flip-flop is on a first integrated circuit and said second flip-flop is on a second integrated circuit. 
     
     
       23. The DE-type flip-flop of claim 20, wherein said DE-type flip-flop and said second flip-flop are on a single circuit board. 
     
     
       24. The DE-type flip-flop of claim 20, wherein said DE-type flip-flop is on a first circuit board and said second flip-flop is on a second circuit board. 
     
     
       25. The DE-type flip-flop of claim 20, wherein said second flip-flop data output terminal of said second flip-flop is coupled to said DE data input terminal through at least one intermediate gate. 
     
     
       26. A method of eliminating a hold time violation in a flip-flop having a flip-flop input terminal, a flip-flop output terminal, and a flip-flop clock input terminal, wherein a data input line is coupled to said flip-flop input terminal, said method comprising: decoupling said data input line from said flip-flop input terminal;   coupling a latch output terminal of a latch to said flip-flop input terminal;   coupling said data input line to a latch input terminal of said latch wherein a data input signal on said data input line is stored in said latch a predetermined fraction of a clock input signal clock period before a first active edge of said clock input signal: said data input signal is applied on flip-flop output terminal in response to said first active edge: and said data input signal is maintained on said flip-flop output terminal for said first clock input signal clock period.   
     
     
       27. The method of eliminating a hold time violation in a flip-flop of claim 26, further comprising: coupling a latch enable terminal of said latch to said flip-flop clock input terminal.   
     
     
       28. A method to eliminate hold time violations in a flip-flop comprising: replacing said flip-flop with a DE-type flip-flop.   
     
     
       29. A method to create an integrated circuit design free of hold time violations comprising: identifying a hold time violation; and   inserting a DE-type flip-flop macrocell into said integrated circuit design, such that said hold time violation is eliminated.   
     
     
       30. The method to create an integrated circuit design in claim 29, wherein said DE-type flip-flop macrocell replaces a standard flip-flop macrocell. 
     
     
       31. The method to create an integrated circuit design in claim 29, wherein said DE-type flip-flop macrocell has a DL-type flip-flop area requirement equal to a standard flip-flop macrocell area requirement of said standard flip-flop macrocell.