Hybrid static RAM circuit

Abstract

A hybrid memory provides both protected and unprotected storage arrays within a common device. The memory includes shared resources including address decoding, data input and output paths and power supply. Three memory arrays provide the storage capacity in which a first memory serves as unprotected memory and a second and third provide storage for data and error correction codes, respectively.

We claim: 
     
       1. A hybrid computer memory comprising: a silicon surface;   a first memory array on the surface, having a capacity of 8 k by 8-bits and including: a first write enable connection;   a first input port having eight data connections; and   a first output port having eight data connections; and     the first memory array is operatively coupled to an address decoder; and   a second memory array on the surface, having a capacity of 16 k by 8-bits and operatively coupled to all of the following: the first write enable connection;   the first input port;   the first output port; and   the address decoder; and       a third memory array on the surface, having a capacity of 16 k by 4-bits and comprising: a second write enable connection;   a second input port having four data connections; and   a second output port having four data connections; and     the third memory array is operatively coupled to the address decoder and stores error correction code data.