Floating-point division and squareroot circuit with early determination of resultant exponent

Abstract

A circuit calculates the exact biased resultant exponent before calculating the resultant mantissa of a division operation. The circuit includes a carry-save adder, a conditional-sum adder, a multiplexer and a comparator. The conventional carry-save adder receives the biased exponent of the dividend (e1), the one's complement of the biased exponent of the divisor (˜e2), and the bias. The conditional-sum adder receives the sum and carry resultants of the carry-save adder, outputting {er0=e1+(˜e2)+bias} and {er1=e1+(˜e2)+bias+1}. The comparator controls the multiplexer to respectively select as the resultant exponent either er0 or er1 when the fraction of the dividend is less than or greater than or equal to the fraction of the divisor. A circuit for determining the resultant exponent of a squareroot operation includes a conditional-sum adder, a multiplexer and a selection logic circuit. The conditional-sum adder receives ½ of e2 and an adjusted bias. The adjusted bias is ½ of the bias (incremented if e2 is odd), causing the conditional-sum adder to output {er0=½e2+adjusted bias} and {er1=½e2+adjusted bias+1}. The selection logic controls the multiplexer to select er0, except in the case in which all three of the following conditions exist: (i) the fraction of the operand has no zeros; (ii) the squareroot operand is even; and (iii) the rounding mode is rounding to positive infinity.

The embodiments of the invention in which an exclusive property or privilege is claimed are defined as follows:  
     
       1. A circuit for determining a resultant exponent of a floating-point division operation of a dividend and divisor, the dividend and divisor each having a fraction and a biased exponent, the circuit comprising: 
       an adder circuit configured to receive the biased dividend exponent (e1), a one's complement of the biased divisor exponent ( ˜ e2) and a bias, wherein said adder circuit generates output sums er0 and er1, wherein sum er0 is equal to e1 +( ˜ e2)+bias, and sum er‘b is equal to er0+1;  
       a multiplexer coupled to receive the sums er0 and er1 from said adder circuit; and  
       a selection logic circuit coupled to said multiplexer, and coupled to receive the dividend fraction and the divisor fraction, wherein said selection logic circuit causes said multiplexer to select the sum er0 when the dividend fraction is less than the divisor fraction without waiting for a result of a mantissa computation.  
     
     
       2. The circuit of claim  1  wherein said selection logic causes said multiplexer to select the sum er1 when the dividend fraction is greater than or equal to the divisor fraction. 
     
     
       3. The circuit of claim  2  wherein said selection logic comprises a comparator coupled to receive the divisor fraction and the dividend fraction. 
     
     
       4. The circuit of claim  1  wherein said adder circuit comprises a carry-save adder and a conditional-sum adder. 
     
     
       5. The circuit of claim  4  wherein said carry-save adder is coupled to receive the biased dividend exponent (e1), the one's complement of the biased divisor exponent ( ˜ e2) and the bias. 
     
     
       6. The circuit of claim  1  further comprising a underflow detector and an overflow detector, said underflow and overflow detectors coupled to receive the sum selected by said multiplexer. 
     
     
       7. The circuit of claim  1  further comprising a first and second underflow detectors and a first and second overflow detectors, said first underflow and overflow detectors coupled to receive the sum er0 from said adder circuit, and said second underflow and overflow detectors coupled to receive the sum er1 from said adder circuit. 
     
     
       8. A circuit for determining a resultant exponent of a floating-point squareroot operation of an operand having a fraction and a biased exponent (e2), the circuit comprising: 
       an adder circuit configured to receive e2 and a constant B, wherein said constant B is a bias when e2is even and the bias+1 when e2 is odd wherein said adder is configured output sums er0 and er1, wherein er0 is equal to ½(e2+B), and er1 is equal to er0+1;  
       a multiplexer coupled to receive the sums er0 and er1 from said adder circuit; and  
       a selection logic circuit coupled to said multiplexer, wherein said selection logic circuit is configured to cause said multiplexer to select the sum er1 when the fraction of the operand has no zeros, e2 is even, and said circuit is configured in a round to positive infinity mode.  
     
     
       9. The circuit of claim  8  wherein said selection logic circuit is further configured to select the sum er1 only when the fraction of the operand has no zeros, e2 is even, and said circuit is configured in a round to positive infinity mode. 
     
     
       10. The circuit of claim  8  wherein said selection logic circuit is further configured to select the sum er0 when any of the following conditions are true: the operand has a zero, e2 is odd, or said circuit is not configured in the round to positive infinity mode. 
     
     
       11. The circuit of claim  8  wherein said adder circuit comprises a conditional-sum adder. 
     
     
       12. A circuit for determining a resultant exponent of a floating-point division operation during a division mode, a floating-point squareroot operation during a squareroot mode and a floating-point multiplication operation during a multiplication mode, each operand of the division, squareroot and multiplication operations having a normalized mantissa and a biased exponent, each mantissa having a fraction, the circuit comprising: 
       a first multiplexer configured to receive the biased exponent (e1) of the first operand and a zero, wherein said first multiplexer is selectably configured to provide as an output operand at an output port of said first multiplexer either zero during the squareroot mode or e1 during the division and multiplication modes;  
       a second multiplexer configured to receive the biased exponent (e2) of the second operand, ½e2, and a one's complement of e2 (˜e2), wherein said second multiplexer is selectably configured to provide as an output operand at an output port of said second multiplexer either e2 during the multiplication mode, ½e2 during the squareroot mode or ˜e2 during the division mode;  
       a third multiplexer configured to receive constants B 1 -B 4 , B 1  being equal to a bias, B2 being equal to the ½(bias), B 3  being equal to ½(bias+1), and B 4  being equal to a one's complement of the bias, wherein said third multiplexer is selectably configured to provide as an output operand at an output port of said third multiplexer either B 1  during the division mode, B 2  during the squareroot mode when e2 is even, B 3  during the squareroot mode when e2 is odd, and B 4  during the multiplication mode;  
       an adder circuit having first, second and third input ports respectively coupled to said output ports of said first, second and third multiplexers, wherein said adder circuit is configured output sums er0 and er1, wherein er0 is equal to a sum of the output operands of said first, second and third multiplexers, and wherein er1 is equal to er0+1;  
       a fourth multiplexer coupled to receive er0 and er1 from said adder circuit; and  
       a selection logic circuit coupled to said fourth multiplexer, wherein said selection logic circuit is configured to cause said fourth multiplexer to select the sum er1 when:  
       the first operand's fraction is greater than or equal to the second operand's fraction when said circuit is in the division mode,  
       the second operand's fraction has no zeros, e2 is even, and said circuit is configured in the squareroot mode with a round to positive infinity rounding mode, and  
       a product of the mantissas of the first and second operands is greater than or equal to two when the circuit is in the multiplication mode.  
     
     
       13. The circuit of claim  12  wherein said adder circuit comprises a carry-save adder and a conditional-sum adder. 
     
     
       14. The circuit of claim  12  wherein said selection logic circuit comprises a comparator configured to receive the fractions of the operands during the division mode. 
     
     
       15. The circuit of claim  12  wherein said selection logic circuit further comprises a decoder configured to receive the fraction of the second operand, a first signal, and a second signal, said first signal having a logic one value when the circuit is in the round to positive infinity rounding mode, and said second signal having a logic one value when e2 is even. 
     
     
       16. The circuit of claim  12  further comprising first and second underflow detectors and first and second underflow detectors, said first underflow and overflow detectors coupled to receive er0 from said adder circuit, and said second underflow and overflow detectors coupled to receive er1 from said adder circuit. 
     
     
       17. The circuit of claim  12  wherein the bias is equal to 127 when the circuit is operating in a single precision mode and  1023  when the circuit is operating in a double precision mode.