Analog video processor

Abstract

An analog video processor is disclosed for coupling a CCD target acquisition and tracking seeker to a microcomputer via a video preprocessor, having a CCD automatic light control circuit, a video automatic gain control circuit, and a TV monitor/display circuit, and via a video processor, having a target acquisition mode gradient processor circuit, to detect target edge sharpness, a target tracking mode contrast processor circuit to detect targets via video amplitude, and an output control circuit, to convert analog and asynchronous target signatures to synchronous target edges for input to the microcomputer.

What is claimed is:  
     
       1. An analog video processor (AVP) in combination with a charge coupled device (CCD) camera; servo motors for orientation control of said camera; a microcomputer (μC) which inputs and outputs from said servo motors and which provides a tracking gate pass signal, a background clamp signal, an add contrast signal, and a whie select signal; and a video monitor (VM), said AVP including a video preprocessor (VPP) providing a delayed vertical sync (DVS) signal and having inputs and outputs from said CCD camera and said μC, and outputting to said VM and having: 
       an automatic light control (ALC) circuit having inputs and outputs from said CCD camera;  
       an automatic gain control (AGC) circuit inputting from said CCD camera; and  
       a display (DP) circuit outputting to said VM and inputting from said μC and said CCD camera,  
       and a video processor (VP) which inputs from said AGC, said VPP, and said μC and which provides a tracker video output signal and which comprises: 
       a gradient processor (GP) circuit inputting from said AGC circuit and including:  
       an analog delay inputting said tracker video signal;  
       a first GP amplifier inputting from said analog delay and inputting said tracker video signal;  
       a GP amplifier/lowpass filter (LPF) inputting from said first GP amplifier;  
       a GP analog video switch (GPAVS) inputting from said GP amplifier/LPF;  
       a GP current amplifier inputting from said GPAVS;  
       a positive/maximum peak detector inputting from said GP current amplifier;  
       a negative/minimum peak detector inputting from said GP current amplifier;  
       a GP quad analog SPST switch inputting from said positive and negative peak detectors and switched by said DVS;  
       a first GP buffer inputting from said positive peak detector through said GP quad analog switch;  
       a second GP buffer inputting from said negative peak detector through said GP quad analog switch;  
       a third GP buffer inputting from said first GP buffer;  
       a fourth GP buffer coupled inputting from said second GP buffer;  
       a first GP comparator inputting from said GP current amplifier and said third GP buffer; and  
       a second GP comparator inputting from said GP current amplifier and said fourth GP buffer,  
       a contrast processor (CP) circuit inputting from said AGC circuit and including:  
       a CP analog video switch (CPAVS) switched by said background clamp signal;  
       a CP sample and hold buffer inputting said tracker video signal through said CPAVS;  
       a CP difference amplifier/LPF inputting from said CP sample and hold buffer and inputting said tracker video signal;  
       a contrast threshold adjustment (CTA);  
       a CP inverter/LPF inputting from said CTA;  
       a first CP comparator inputting from said CP difference amplifier and said CTA; and  
       a second CP comparator inputting from said CP difference amplifier and said CP inverter,  
       an output control (OC) circuit inputting from said GP circuit, inputting from said CP circuit, inputting said add contrast signal and said white select signal, and outputting and inputting from said μC and including:  
       a first exclusive OR gate having said white select signal as one input;  
       a first OC NAND gate having one input from said first exclusive OR gate and having said add contrast signal as another input;  
       a second exclusive OR gate having said white select signal as one input;  
       a second OC NAND gate having one input from said second exclusive OR gate and having said add contrast signal as another input;  
       a dual one shot inputting from said first and second OC NAND gates;  
       a third OC NAND gate inputting from said one shot;  
       an OC JK flip flop inputting from said third OC NAND gate, having complemented outputs to said first and second exclusive OR gates, and inputting said tracking gate pass signal;  
       a first OC inverter inputting from said first CP comparator;  
       a second OC inverter inputting from said second CP comparator; and  
       a dual four to one multiplexer inputting from said first and second OC inverters, inputting from said first and second CP comparators, inputting said add contrast and said white select signals, and outputting to said one shot.