Acquisition of extended display identification data (EDID) in a display controller in a power up mode from a power down mode

Abstract

A video controller having a processor for processing executable instructions and associated data and a number of data ports, a method of acquiring extended display identification data (EDID) by a requesting one of the data ports is described. When on-board power supply is activated, an off-board power supply is deactivated and then the now active on-board power supply provides power to a memory device used to store the EDID and the executable instructions and associated data and to an on-board clock circuit capable of providing a high frequency clock signal. The on-board clock circuit, in turn, provides the high frequency clock signal from the on-board clock circuit to the memory device and if a memory read operation had been in progress when the on-board power supply was activated, then the memory read operation is completed.

1. In a video controller having a processor for processing executable instructions and associated data and a number of data ports, a method of acquiring extended display identification data (EDID) by a requesting one of the data ports, comprising:
 activating an on-board power supply;  
 disconnecting an off-board power supply arranged to provide power to a memory device used to store the EDID and the executable instructions and associated data when the on-board power supply is activated;  
 providing power from the on-board power supply to the memory device used to store the EDID and the executable instructions and associated data;  
 providing power from the on-board power supply to an on-board clock circuit capable of providing a high frequency clock signal;  
 providing the high frequency clock signal from the on-board clock circuit to the memory device; and  
 if a memory read operation was in progress when the on-board power supply was activated, then completing the memory read operation.  
 
     
     
       2. A method as recited in  claim 1 ; further comprising:
 when the on-board power supply is determined to be inactive, then providing power to the memory device by the off-board power supply.  
 
     
     
       3. A method as recited in  claim 2 , wherein the off-board power supply is connected to the memory device by way of the requesting one of the data ports. 
     
     
       4. A method as recited in  claim 1 , wherein when the on-board power supply is determined to be inactive, then activating a low power clock circuit arranged to provide a low frequency clock signal. 
     
     
       5. A method as recited in  claim 4 , further comprising:
 providing the low frequency clock signal to the memory device; and  
 providing the requested EDID from the memory device using the low frequency clock signal.  
 
     
     
       6. Computer program product for acquiring extended display identification data (EDID) by a requesting data ports in video controller having a processor arranged to process computer program product and associated data, comprising:
 computer code for activating an on-board power supply;  
 computer code for disconnecting an off-board power supply when the on-board power supply is activated;  
 computer code for providing power from the on-board power supply to a memory device used to store the EDID and the executable instructions and associated data when the on-board power supply is active;  
 computer code for providing power from the on-board power supply to an on-board clock circuit capable of providing a high frequency clock signal;  
 computer code for providing the high frequency clock signal from the on-board clock circuit to the memory device;  
 computer code for determining if a memory read operation had been in progress when the on-board power supply was activated;  
 computer code for completing the memory read operation; and  
 computer readable medium for storing the computer code.  
 
     
     
       7. Computer program product as recited in  claim 6 , further comprising:
 computer code for providing power to the memory device by the off-board power supply when the on-board power supply is determined to be inactive.  
 
     
     
       8. Computer program product as recited in  claim 7 , wherein the off-board power supply is connected to the memory device by way of the requesting data port. 
     
     
       9. Computer program product as recited in  claim 6 , further comprising:
 computer code for activating a low power clock circuit to provide a low frequency clock signal when the on-board power supply is determined to be inactive.  
 
     
     
       10. Computer program product as recited in  claim 9 . further comprising:
 computer code for providing the low frequency clock signal to the memory device; and  
 computer code for providing the requested EDID from the memory device using the low frequency clock signal.  
 
     
     
       11. An EDID compliant flat panel display controller, comprising:
 a processor for processing executable instructions and associated data;  
 an on-board power supply arranged to provide power to the display controller when requested;  
 a number of data ports coupled to an external video source;  
 a memory device for storing both the executable instruction and associated data and the EDID;  
 a bridge section coupled between the data ports and the memory device; and  
 a switch circuit arranged to direct power provided by the video source to the memory device in a first mode and to direct power provided by the on-board power supply in a second mode.  
 
     
     
       12. A flat panel controller as recited in  claim 11 , wherein the first mode is a power_off mode wherein the on-board power supply is inactive and wherein the video source provides power to the memory device by way of the switch circuit. 
     
     
       13. A flat panel controller as recited in  claim 12 , wherein the second mode is a power_on mode wherein the on-board power supply is active and wherein the on-board power supply supplies power to the memory device by way of the switch circuit. 
     
     
       14. A flat panel controller as recited in  claim 13 , further comprising:
 a high frequency clock circuit coupled to the on-board power supply arranged to provide a high frequency clock signal only when the on-board power supply is active; and  
 a low frequency clock circuit coupled to the video source by way of the switch when the on-board power supply is inactive arranged to provide a low frequency clock signal to the memory device thereby providing the requesting port access to the memory device when the on-board power supply is inactive or active.