Analog multiplexer

Abstract

A fast analog multiplexer is disclosed which utilizes a plurality of paral MOSFETs coupled to a plurality of parallel analog inputs, the gates of said MOSFETs being controlled by a binary decoder to allow passage of only on analog voltage to be summed by an op amp while concomitantly shorting other analog voltages to ground, thereby attenuating the delaying summed capacitive effects of stacked parallel MOSFETs.

What is claimed is: 
     
       1. An analog multiplexer, comprising: an op amp having an inverted and noninverting input and an output and further having a summing node coupled to said inverting input and a feedback resistor coupling said output to said inverting input;   at least two analog inputs each having a resistance coupling to said summing nodes;   an equal number of MOSFETs as said analog inputs, each said MOSFET having a drain, a source, a substrate, and a gate, said drain of each said MOSFET being connected to said resistance coupling, said source of each said MOSFET being only coupled to a common signal return, and said substrate of each said MOSFET being coupled to power source;   decoder-driving means having a plurality of digital inputs and a plurality of driver outputs, said driver outputs being equal in number to said MOSFETs, each said driver output being coupled to said gates of each said respective MOSFET, for receiving a digital command input, and for driving one said gate of each said MOSFET low and driving said gates of all other MOSFETs high.