Row-address-decoder-driver circuit

Abstract

A static noninverting driver circuit is used with a standard static address-row-decoder circuit in order to provide capacitance load drive capability and relatively high-speed operation. The driver circuit uses n-channel enhancement and depletion mode field effect transistors and a feedback bootstrap capacitor to achieve low power-high speed operation with a full VDD output high level.

What is claimed is: 
     
       1. Circuitry comprising: a first inverter circuit having an input terminal and an output terminal;   a second inverter circuit having an input terminal and an output terminal;   a third inverter circuit having first and second input terminals and an output terminal;   a first capacitor circuit means having first and second terminals;   a potential setting circuit means coupled to the first terminal of the capacitor circuit means for selectively setting the potential thereof to a first preselected level;   the input terminal of the first inverter circuit being coupled to a circuitry input terminal;   the output terminal of the first inverter circuit being coupled to the input terminal of the second inverter circuit and to the first input terminal of the third inverter circuit;   delay circuit means being coupled by a first terminal to the output terminal of the firt inverter circuit and being coupled by a second terminal to the second terminal of the capacitor circuit means; and   a coupling/decoupling switching device having a control terminal and first and second output terminals, the first output terminal thereof being coupled to the first terminal of the capacitor circuit means and the second output terminal thereof being coupled to the second input terminal of the third inverter circuit and to the output terminal of the second inverter circuit and the control terminal thereof being connected to a potential source that allows an increase in potential on the first terminal of the capacitor circuit means to be coupled to the second output terminal of the switching device, and wherein said second inverter includes a switching device (T22, T220) that is connected to the output terminal of said second inverter and to a voltage source (VDD) that tends to bias said coupling/decoupling switching device towards conduction.   
     
     
       2. The circuitry of claim 1 wherein: the first inverter circuit comprises essentially first and second switching devices each having a control terminal and first and second output terminals;   the second inverter circuit comprises essentially third and fourth switching devices each having a control terminal and first and second output terminals;   the third inverter comprises essentially fifth and sixth switching devices each having a control terminal and first and second output terminals;   the control terminal of the second switching device being coupled to the circuitry input terminal;   the control terminal of the fifth switching device being coupled to the second output terminal of the third switching device, to the first output terminal of the fourth switching device, to the output terminal of the second inverter circuit, and to the second output terminal of the coupling/decoupling switching device;   the first capacitor circuit means comprises a seventh switching device having a control terminal and first and second output terminals;   the potential setting circuit means comprises an eighth switching device having a control terminal and first and second output terminals; and   the second output terminal of the eighth switching device being coupled to the control terminal of the seventh switching device, and to the first output terminal of the coupling/decoupling switching device.   
     
     
       3. The circuitry of claim 1 wherein the delay circuit means comprises the first and third inverter circuits, the output terminal of the third inverter circuit serves as the second terminal of the delay circuit means, and the input terminal of the first inverter circuit serves as the first terminal of the delay circuit means. 
     
     
       4. The circuitry of claim 2 further comprising: a fourth inverter circuit having first and second input terminals and an output terminal;   the first input terminal of the fourth inverter circuit being coupled to the output terminal of the first inverter circuit;   the output terminal of the fourth inverter circuit being coupled to the first and second output terminals of the seventh switching device; and   the second input terminal of the fourth inverter circuit being coupled to the output terminal of the second inverter circuit.   
     
     
       5. The circuitry of claim 4 wherein the first and fourth inverter circuits comprise the delay circuit means, with the first terminal of the delay circuit means being the input terminal of the first inverter circuit, and with the output terminal of the fourth inverter circuit being the second terminal of the delay circuit means. 
     
     
       6. The circuitry of claim 5 wherein: the fourth inverter circuit comprises ninth and tenth switching devices which each comprise a control terminal and first and second output terminals;   the control terminal of the tenth switching device being coupled to the output terminal of the first inverter circuit;   the control terminal of the ninth switching device being coupled to the second output terminal of the third switching device; and   the second output terminal of the ninth switching device and the first output terminal of the tenth switching device being coupled to the first and second output terminals of the seventh switching device.   
     
     
       7. The circuitry of claim 6 further comprising: a second capacitor circuit means having a first terminal coupled to the circuitry input terminal and having a second terminal coupled to the control terminal of the third switching device;   eleventh and twelfth switching devices each having a control terminal and first and second output terminals;   the second output terminal of the eleventh switching device being coupled to the control terminal of the third switching device; and   the second output terminal of the twelfth switching device being coupled to the output terminal of the third inverter circuit.   
     
     
       8. The circuitry of claim 7 wherein: the second capacitor circuit means comprises a thirteenth switching device having a control terminal and first and second output terminals;   the control terminal of the thirteenth switching device being coupled to the control terminal of the third switching device; and   the first and second output terminals of the thirteenth switching device being coupled together to the circuitry input terminal.   
     
     
       9. The circuitry of claim 8 wherein all switching devices are field effect transistors. 
     
     
       10. The circuitry of claim 9 wherein: the second, third, fourth, fifth, sixth, ninth, tenth, and eleventh transistors are n-channel type enhancement mode insulated gate field effect transistors, and the coupling/decoupling transistor, the first, seventh, eighth, twelfth, and thirteenth transistors are n-channel type depletion mode insulated gate field effect transistors, wherein each of said transistors has a drain as the first output terminal thereof and a source as the second output terminal thereof;   the gate of the transistor which comprises the coupling/decoupling switching device is coupled to the source thereof;   the seventh switching device has the drain and source thereof coupled together and serving as the second terminal of the first capacitor circuit means and has the gate thereof serving as the first terminal of the first capacitor circuit means;   the thirteenth switching device has the drain and source thereof coupled together and serving as the second terminal of the second capacitor means and has the gate thereof serving as the first terminal of the second capacitor circuit means;   the eighth switching device has the gate thereof coupled to the output terminal of the first inverter circuit; and   the transistor which comprises the twelfth switching device has the gate and source thereof coupled together.   
     
     
       11. The circuitry of claim 10 further comprising a row-address-decoder circuit having an output terminal coupled to the circuitry input terminal. 
     
     
       12. Circuitry comprising: a first inverter circuit having an input terminal and an output terminal;   a second inverter circuit having first and second input terminals and an output terminal;   a first capacitor circuit means having first and second terminals;   a potential setting circuit means coupled to the first terminal of the capacitor circuit means for selectively setting the potential thereof to a first preselected level;   the input terminal of the first inverter circuit and the first input terminal of the second inverter circuit being coupled to a circuitry input terminal;   the output terminal of the first inverter circuit being coupled to the second input terminal of the second inverter circuit;   delay circuit means being coupled by a first terminal to the input terminal of the first inverter circuit and being coupled by a second terminal to the second terminal of the capacitor circuit means; and   a coupling/decoupling switching device having a control terminal and first and second output terminals, the first output terminal thereof being coupled to the first terminal of the capacitor circuit means and the second output terminal thereof being coupled to the output terminal of the first inverter circuit and to the second input terminal of the second inverter circuit and the control terminal thereof being connected to a potential source that allows an increase in potential on the first terminal of the capacitor circuit means to be coupled to the second output terminal of the switching device, and wherein said first inverter includes a switching device (T22, T220) that is connected to the output terminal of said first inverter and to a voltage source (VDD) that tends to bias said coupling/decoupling switching device towards conduction.   
     
     
       13. The circuitry of claim 12 wherein said coupling/decoupling switching device is a depletion mode insulated gate field effect transistor having a source and a drain, wherein the gate thereof is connected to the source thereof. 
     
     
       14. The circuitry of claim 12 wherein said coupling/decoupling switching device is an enhancement mode insulated gate field effect transistor having a source and a drain, wherein the gate thereof is connected to the drain thereof. 
     
     
       15. The circuitry of claim 12 wherein said coupling/decoupling switching device is an enhancement mode insulated gate field effect transistor wherein a voltage pulse circuitry is said potential source.