Floating gate memory with improved dielectric

Abstract

The dielectric between the floating gate and the control gate, in an EEPROM or other floating gate memory is made by forming an oxide/nitride stack over the (first polysilicon) control gate. This dielectric not only provides a very high specific capacitance, which is desired to provide tight coupling of the control to the floating gate, but also provides excellent dielectric integrity. Moreover, the thickness of this dielectric layer does not exhibit any uncontrolled increase during exposure to second gate oxidation. Thus, the polysilicon-to-polysilicon dielectric is not only of high specific capacitance and high integrity, it is also very uniform.

What is claimed is: 
     
       1. A floating gate memory .[.cell.]. .Iadd.device .Iaddend.comprising: (a) a silicon substrate;   (b) a plurality of polysilicon insulated floating gates .Iadd.overlying a first gate insulating layer .Iaddend.on said silicon substrate, said floating gates defining respective channel regions beneath said respective floating gates in the surface of said substrate;   .Iadd.(c) at least one other transistor gate overlying a second gate insulating layer on said silicon substrate; .Iaddend.   .[.(c).]. (.Iadd.d) .Iaddend.a plurality of polysilicon control gates over respective ones of said floating gates;   .[.(d).]. (.Iadd.e) .Iaddend.a composite dielectric comprising both silicon nitride and silicon dioxide disposed between said control gates and said respective floating gates;   .[.(e).]. (.Iadd.f) .Iaddend.a plurality of source and drain regions respectively separated by respective ones of said channel regions; and   .[.(f).]. (.Iadd.g) .Iaddend.means for applying a write voltage to a selected one of said control gates.[.,.]..Iadd.; .Iaddend.   .[.(g).]. (.Iadd.h) .Iaddend.said voltage being about 15 volts .[.when said dielectric is about 400 angstroms, said voltage varying therefrom proportionally with the thickness of said dielectric.]. .Iadd.when the thickness of said second gate insulating layer is about 400 angstroms, 21 volts when the thickness of said second gate insulating layer is about 600 angstroms, said voltage varying therefrom proportionally with the thickness of said second gate insulating layer. .Iaddend.   
     
     
       2. The device of claim 1 further comprising means for applying a read voltage between a selected one of said sources and said respective corresponding drain. .[. 
     
     
       3.  A floating gate memory cell, comprising: (a) a silicon substrate;   (b) a plurality of polysilicon insulated floating gates on said silicon substrate, said floating gates defining respective channel regions beneath said respective floating gates in the surface of said substrate;   (c) a plurality of polysilicon control gates over respective ones of said floating gates;   (d) a composite dielectric comprising both silicon nitride and silicon dioxide disposed between said control gates and said respective floating gates;   (e) a plurality of source and drain regions respectively separated by respective ones of said channel regions; and   (f) means for applying a write voltage to a selected one of said control gates,   (g) said voltage being about 21 volts when said dielectric is about 600 angstroms, said voltage varying therefrom proportionally with the thickness of said dielectric..]. .[.4. The device of claim 3 further comprising means for applying a read voltage between a selected one of   
     
     
        said sources and said respective corresponding drain..]. .Iadd.5.  The device of claim 1, wherein the thickness of said first insulating layer is about the thickness of said second insulating layer. .Iaddend. .Iadd.6. The device of claim 1, wherein said plurality of polysilicon insulated floating gates is formed from a first layer of polysilicon and said at least one other transistor gate and said polysilicon control gates are formed from a second layer of polysilicon. .Iaddend. .Iadd.7. A floating gate memory device, comprising: (a) a silicon substrate;   (b) a plurality of polysilicon insulated floating gates overlying a first insulating layer on said silicon substrate, said floating gates defining respective channel regions beneath said respective floating gates in the surface of said substrate;   at least one other transistor gate overlying a second insulating layer on said silicon substrate,   (c) a plurality of polysilicon control gates over respective ones of said floating gates;   (d) a composite dielectric comprising both silicon nitride and silicon dioxide disposed between said control gates and said respective floating gates, said composite dielectric being thinner than said second insulating layer;   a plurality of source and drain regions respectively separated by respective ones of said channel regions;   and means for applying a write voltage to a selected one of said control gates and means for applying a voltage of a magnitude of about said write   
     
     
        voltage to said at least one other transistor gate..Iaddend. .Iadd.8.  The device of claim 7, wherein the thickness of said first insulating layer is about the thickness of said second insulating layer..Iaddend. .Iadd.9. The device of claim 7 further comprising means for applying a read voltage between a selected one of said sources and said respective corresponding drain..Iaddend. .Iadd.10. The device of claim 7, wherein said plurality of polysilicon floating gates is formed from a first layer of polysilicon and said at least one other transistor gate and said polysilicon control gates are formed from a second layer of polysilicon..Iaddend.