Method and apparatus for bit operational process

Abstract

A bit operation processor having a first address operation unit for updating the address of data in units of a byte or multiple bytes for performing operation in units of a byte or multiple bytes. A second address operation unit for updating the address of data in units of a bit or multiple bits, an address controller operating on the first address operation unit to advance the address in response to the result of address advancement by the second address operation unit. Fetching byte-wide data for operation as addressed by the first address operation unit, whereby operation between data of any number of bits at any positions in byte blocks is controlled simply and fast.

We claim: 
     
       1. A bit operation processing method for processing operand data and operating data stored in a memory comprising: (a) a first step of incrementing in units of an integral number of bytes, addresses of said operand data and said operating data to be processed in units of an integral number of bytes independent from each other;   (b) a second step of incrementing addresses of data of said operand data and said operating data in units of an integral number of bits independent from each other;   (c) a third step of causing said first step to increment addresses on the basis of the result of address incrementing in said second step; and   (d) a fourth step of retrieving stored operand data and operating data in units of a byte at locations in memory designated by addresses produced in said first step, and for performing arithmetic or logic operations using the retrieved stored operand data and operating data.   
     
     
       2. A bit operation processing method for processing operand data and operating data stored in a memory comprising: (a) a first step of incrementing in units of an integral number of bytes, addresses of said operand data and said operating data to be processed in units of an integral number of bytes independent from each other;   (b) a second step of incrementing addresses of data of said operand data and said operating data in units of an integral number of bits;   (c) a third step of causing said first step to increment addresses on the basis of the result of address incrementing in said second step; and   (d) a fourth step of retrieving stored operand data and operating data i units of a byte at locations in memory designated by addresses produced in said first step, and for performing arithmetic or logic operations using the retrieved stored operand data and operating data;   wherein said third step includes generating a starting bit position for a subsequent operation based on the result of addition of a current starting bit position to a number of operation bits of data defined within said unit of data implemented by said second step.   
     
     
       3. A bit operation processing method for processing operand data and operating data stored in a memory comprising: (a) a first step of incrementing in units of an integral number of bytes, addresses of said operand data and said operating data to be processed in units of an integral number of bytes independent from the other;   (b) a second step of incrementing addresses of data of said operand data and said operating data in units of an integral number of bits;   (c) a third step of causing said first step to increment addresses on the basis of the result of addresses incrementing in said second step; and   (d) a fourth step of retrieving stored operand data and operating data in units of a byte at locations in memory designated by addresses produced in said first step, and for performing arithmetic or logic operations using the retrieved stored operand data and operating data;   wherein said third step includes controlling the address incrementing in said first step in response to carry information created in said second step.   
     
     
       4. A bit operation processing method for processing operand data and operating data stored in a memory comprising: (a) a first step of incrementing in units of an integral number of bytes, addresses of said operand data and said operating data to be processed in units of an integral number of bytes independent from the other;   (b) a second step of incrementing addresses of data of said operand data and said operating data in units of an integral number of bits;   (c) a third step of causing said first step to increment addresses on the basis of the result of address incrementing in said second step; and   (d) a fourth step of retrieving stored operand data and operating data in units of a byte at locations in memory designated by addresses produced in said first step, and for performing arithmetic or logic operations using the retrieved stored operand data and operating data;   wherein memory address control is implemented in said first step and internal data address control is implemented in said second step.   
     
     
       5. A bit operation processing method for processing operant data and operating data stored in a memory comprising: (a) a first step of incrementing in units of an integral of bytes, addresses of said operand data and said operating data to be processed in units of an integral number of bytes independent from each other;   (b) a second step of incrementing addresses of data of said operand data and said operating data in units of an integral number of bits;   (c) a third step of causing said first step to increment addresses on the basis of the result of address incrementing in said second step; and   (d) a fourth step of retrieving stored operand data and operating data i units of a byte at locations in memory designed by addresses produced in said first step, and for performing arithmetic or logic operations using the retrieved stored operand data and operating data;   wherein said fourth step implements control for the starting bit position of said operating data and control for the starting bit position of said operand data independently from each other.   
     
     
       6. A method according to claim 5, wherein said operation bit width, said starting bit position of operating data and said starting bit position of operand data are identical to those treated in said step 2, and said values are incremented by "1". 
     
     
       7. A bit operation processing method for processing operand and operating data stored in a memory comprising: (a) a first step of incrementing in units of an integral number of bytes, addresses of said operand data and said operating data to be processed in units of an integral number of bytes independent from each other;   (b) a second step of incrementing addresses of data of said operand data and said operating data in units of an integral number of bits;   (c) a third step of causing said first step to increment addresses on the basis of the result of address incrementing in said second step; and   (d) a fourth step of retrieving stored operand data and operating data in units of a byte at locations in memory designated by addresses produced in said first step, and for performing arithmetic or logic operations using the retrieved stored operand data and operating data;   wherein said fourth step comprises   (a) a fifth step of slicing part of the operating data and part of the operand data;   (b) a sixth step of performing an operation between sliced operating data and sliced operand data; and   (c) a seventh step of merging resultant data of said sixth step into said operating data or said operand data, and storing the result in the memory.   
     
     
       8. A method according to claim 7, wherein said sixth step comprises adding at least one "0" bit following the lowest-order bit of operating data and operand data so that both data have the same bit width as that of said operation bit width, in response to a test result that the slicing bit width is smaller than said operation bit width. 
     
     
       9. A method according to claim 7, wherein said sixth step comprises adding at least one "0" bit following the lowest-order bit of one of the operating data and the operand data and adding at least one "1" bit following the lowest-order bit of the other of operating data and operand data so that both data have the same bit width as of said operation bit width, in response to a test result that the slicing bit width is smaller than said operation bit width. 
     
     
       10. A method according to claim 7, wherein said sixth step comprises adding a "0" bit or "1" bit following the lowest-order bit of operand data and operating data depending on the type of operation, in response to a test result that the slicing bit width is smaller than said operation bit width. 
     
     
       11. A bit operation processing apparatus having a memory for processing operand data and operating data stored in said memory comprising: (a) first means for producing addresses for addressing stored operand data and operating data in a of an integral number of bytes, said operand data and said operating data being subjected to operation in said units of an integral number of bytes independent from each other;   (b) second means for producing addresses for addressing data of said operand data and said operating data to be processed or in units of an integral number of bits independent from each other;   (c) third means for controlling said second means to increment addresses and for controlling said first means to increment addresses based on the result of address incrementing by said second means; and   (d) fourth means for fetching operand data and operating data in units of a byte from said memory at locations of addresses produced by said first means, and for performing arithmetic or logic operations using said fetched operand data and operating data.   
     
     
       12. A bit operation processing apparatus having a memory for processing operand data and operating data stored in said memory comprising: (a) first means for producing addresses for addressing stored operand data and operating data in units of an integral number of bytes, said operand data and said operating data being subjected to operation in said units of an integral number of bytes independent from each other;   (b) second means for producing addresses for addressing data of said operand data and said operating data in units of an integral number of bits;   (c) third means for controlling said second means to increment addresses and for controlling said first means to increment addresses based on the result of address incrementing by said second means; and   (d) fourth means for fetching operand data and operating data in units of a byte from said memory at locations of addresses produced by said first means, and for performing arithmetic or logic operations using said fetched operand data and operating data;   wherein said third means includes means for controlling said second means to add a number of operation bits within the data length in said units of an integral number of bytes to a value of a current operation starting bit position, thereby generating an operation starting bit position for a subsequent operational process.   
     
     
       13. A bit operation processing apparatus having a memory for processing operand data and operating data stored in said memory comprising: (a) first means for producing addresses for addressing stored operand data and operating data in units of an integral number of bytes, said operand data and said operating data being subjected to operation in said units of an integral number of bytes independent from each other;   (b) second means for producing addresses for addressing data of said operand data and said operating data in units of an integral number of bits;   (c) third means for controlling said second means to increment addresses and for controlling said first means to increment addresses based on the result of address incrementing by said second means; and   (d) fourth means for fetching operand data and operating data in units of a byte from said memory at locations of addresses produced by said first means, and for performing arithmetic or logic operations using said fetched operand data and operating data;   wherein said first means includes means for effecting address incrementing in response to a carry signal from said second means.   
     
     
       14. A bit operation processing apparatus having a memory for processing operand data and operating data stored in said memory comprising: (a) first means for producing addresses for addressing stored operand data and operating data in units of an integral number of bytes, said operand data and said operating data being subjected to operation in said units of an integral number of bytes independent from each other;   (b) second means for producing addresses for addressing data of said operand data and said operating data in units of an integral number of bits;   (c) third means for controlling said second means to increment addresses and for controlling said first means to increment addresses based on the result of address incrementing by said second means; and   (d) fourth means for fetching operand data and operating data in units of a byte from said memory at locations of addresses produced by said first means, and for performing arithmetic or logic operations using said fetched operand data and operating data;   wherein said first means performs address control for said memory and said second means performs address control for internal operation data registers.   
     
     
       15. A bit operation processing apparatus having a memory for processing operand data and operating data stored in said memory comprising: (a) first means for producing addresses for addressing stored operand data and operating data in units of an integral number of bytes, said operand data and said operating data being subjected to operation in said units of an integral number of bytes independent from each other;   (b) second means for producing addresses for addressing data of said operand data and said operating data in units of an integral number of bits;   (c) third means for controlling said second means to increment addresses and for controlling said first means to increment addresses based on the result of address incrementing by said second means; and   (d) fourth means for fetching operand data and operating data in units of a byte from said memory at locations of addresses produced by said first means, and for performing arithmetic or logic operations using said fetched operand data and operating data;   wherein said fourth means comprises a first register for storing a bit address indicating an operation starting bit position of said operating data and a second register for storing a bit address indicating an operating starting bit position of said operand data, said bit addresses of said operating data and said operand data being controlled separately.   
     
     
       16. An apparatus according to claim 15, wherein said second means includes means for storing an advanced bit address in said first register when said second means has calculated said advanced bit address using a content of said first register, or stores an advanced bit address in said second register when said second means has calculated said advanced bit address using a content of said second register. 
     
     
       17. An apparatus according to claim 15, wherein said fourth means fetches data from an external memory at a location of an address produced by said first means when said second means has produced the carry signal in response to a content of said first register, or fetches data from said memory at a location of address produced by said first means when said second means has produced the carry signal in response to a content of said second register, and wherein said fourth means includes means for storing an operation result in said memory at a location of an address prior to incrementing by said first means. 
     
     
       18. An apparatus according to claim 17, wherein said number of operation bits, said operation starting bit position of operating data and said operation starting bit position of operand data are equal to a number of bits which can be treated by said second means, said value of a bit position being always incremented by "1" when said second means is used. 
     
     
       19. A bit operation processing apparatus having a memory for processing operand data and operating data stored in said memory comprising: (a) first means for producing addresses for addressing stored operand data and operating data in units of an integral number of bytes, said operand data and said operating data being subjected to operation in said units of an integral number of bytes independent from each other;   (b) second means for producing addresses for addressing data of said operand data and said operating data in units of an integral number of bits;   (c) third means for controlling said second means to increment addresses and for controlling said first means to increment addresses based on the result of address incrementing by said second means; and   (d) fourth means for fetching operand data and operating data in units of a byte from said memory at locations of addresses produced by said first means, and for performing arithmetic or logic operations using said fetched operand data and operating data;   wherein said fourth means comprises:   (a) means for slicing part of said operating data and part of said operand data;   (b) means for implementing operation between a sliced operating data and a sliced operand data; and   (c) means for merging a resultant data from said operation means into said sliced operating data or sliced operand data and storing a merged data in said memory.   
     
     
       20. An apparatus according to claim 19, wherein said slicing means includes a third register for storing a slicing position of said operating data, a fourth register for storing a slicing position of said operand data and a fifth register for storing a slicing width, and wherein said merging means includes a sixth register for storing a merging bit position and a seventh register for storing a merging width. 
     
     
       21. An apparatus according to claim 20, wherein said operation means appends at least one "0" bit following the lowest order bit position of said sliced operating and operand data so that said data have a same number of bits as a number of operation bits when said slicing width is smaller than the number of operation bits. 
     
     
       22. An apparatus according to claim 20, wherein said operation means appends at least one "0" bit following the lowest bit position of one of said operating data and operand data and appends at least one "1" bit following the lowest bit position of the other so that said data has the same number of bits as the number of operation bits when said slicing width is smaller than the number of operation bits. 
     
     
       23. An apparatus according to claim 20, wherein said operation means appends a "0" bit or "1" bit following the lowest bit position of said operand data and operating data depending on the type of operation when said slicing width is smaller than a number of operation bits. 
     
     
       24. An apparatus according to claim 20, wherein said fifth register and seventh register comprise a common register for implementing slicing and merging of data in a same number of bits. 
     
     
       25. A bit operation processing method for processing operand data and operating data stored in a memory, comprising: a first step for producing memory addresses of data to be subjected to operation processing in units of an integral number of bytes, including a first sub-step of incrementing an address of said operand data and said operating data in units of an integral number of bytes independent from each other, and a second sub-step of incrementing an address of the operand data and the operating data independent from each other;   a second step of starting the address incrementing in said first sub-step on the basis of a result of the address incrementing in said second sub-step; and   a third step of accessing operand data and operating data in said memory at the address produced in said first sub-step, in units of an integral number of bytes, and for performing arithmetic or logic operations using the operand data and said operating data.   
     
     
       26. A bit operation processing method for processing operand and operating data stored in memory, comprising: a first step for producing memory addresses of data to be subjected to operation processing in units of an integral number of bytes, including a first sub-step of incrementing an address of said operand data and said operating data in units of an integral number of bytes independent from each other, and a second sub-step of incrementing an address of data in units of an integral number of bits;   a second step of starting the address incrementing in said first sub-step on the basis of a result of the address incrementing in said second sub-step; and   a third step of accessing operand data and operating data in said memory at the address produced in said first sub-step, in units of an integral number of bytes, and for performing arithmetic or logic operations using the operand data and operating data;   wherein in said second step the value of an operation bit width defined within a range in boundaries of a length of data operated in units of an integral number of bytes, and the value of an operation starting bit position in a current operation process are added to generate an operation starting bit position in the next operation process.   
     
     
       27. A method according to claim 26, wherein the range of the value of said operation bit width, the value of said starting bit position of operating data and the value of said starting bit position of operand data are identical to the range treated in said second sub-step and "1" is added in generation of the operation starting bit using said addresses. 
     
     
       28. A bit operation processing apparatus, having a memory, for processing operand data and operating data stored in said memory, comprising: means for producing memory addresses of said operand data and said operating data to be subjected to processing in units of an integral number of bytes independent from each other, including first means for producing addresses by incrementing an address in units of an integral number of bytes, and second means for producing addresses by incrementing an address of said operand data and said operating data in units of an integral number of bits independent from each other;   third means for controlling the starting of address incrementing in said first means on the basis of a result of address incrementing in said second means; and   fourth means for accessing operand data and operating data in said memory, said operand data and operating data corresponding to the address produced by said first means and for performing arithmetic or logic operations using the accessed operand data and operating data.   
     
     
       29. A bit operation processing apparatus, having a memory, for processing operand data and operating data stored in said memory, comprising: means for producing memory addresses of said operand data and said operating data to be subjected to processing in units of an integral number of bytes independent from each other, including first means for producing addresses by incrementing an address in units of an integral number of bytes, and second means for producing addresses by incrementing an address in units of an integral number of bits;   third means for controlling the starting of address incrementing in said first means on the basis of a result of address incrementing in said second means; and   fourth means for accessing operand data and operating data in said memory, said operand data and operating data corresponding to the address produced by said first means and for performing arithmetic or logic operations using the accessed operand data and operating data;   wherein said third means includes means for adding the value of a width of operation bits defined within a range in boundaries of a length of data operated in units of an integral number of bytes, and the value of an operation starting bit position in a current operation process to generate an operation starting bit position in a subsequent operation process.