Signal controlled waveform recorder

Abstract

A multi-channel electronic waveform recorder, for storing waveform data and time of occurrence information, i.e., a "time-tag", for each stored value of an input waveform, is disclosed. Specifically, each channel of the waveform recorder compares a previously stored value of a corresponding input signal to a current value .Iadd.of that signal.Iaddend., and .[.stores.]. .Iadd.is able to store .Iaddend.the current value whenever the difference between the input signal and the previously stored value is a predetermined amount. .Iadd.Each or any selected sub-set of all the channels, through an appropriate switch setting, can determine points in time when, in response to the difference occurring for that channel, all the channels will simultaneously store the current value of these respective input signals. .Iaddend.

What is claimed is: .[.1. A signal controlled waveform recorder having a plurality of data channels for recording selected portions of the signals supplied to the data channels of said recorder, said recorder comprising; 
     
        .[.1.  A signal controlled waveform recorder having a plurality of data channels for recording selected positions of analog electrical input signals, said recorder comprising: (a) analog to digital converter means responsive to said analog input signal to provide a plurality of digital bits representative of the analog signal amplitudes;   (b) means responsive to said plurality of digital bits and a clock pulse signal providing a latch value substantially equivalent to the values of said analog input signals at the time of the clock pulse signal;   (c) means for producing a digital output signal having substantially the same logical value as those of previously stored values of said analog input signals;   (d) means for comparing the logical values of said latched digital signals and digital output signals and producing control signals responsive to any logical difference therebetween; and   (e) means responsive to said control signals for storing in parallel the latch values representative of said analog input signals..]. .[.12. The invention of claim 11 wherein said recorder further includes means for storing in parallel time-tag values, representing the time of occurrence of an associated latched value stored in said data channels..]. .[.13. The invention of claim 12 wherein said waveform recorder further comprises means connected to each of said data channels and responsive to the control signal generated by any of such data channels for causing at least one of said data channels to store the latched value associated therewith..]. .[.14. The invention of claim 13 wherein means are provided   
     
     
        for playback of said recorded latch values..]. .Iadd.15.  The signal controlled waveform recorder having a plurality of data channels for recording selected portions of a corresponding signal supplied to each one of the data channels, said recorder comprising: means, associated with each one of said data channels and responsive to a corresponding one of a plurality of input signals and a clock pulse, for providing a corresponding one of a plurality of digital signals, wherein each of said digital signals corresponds to an associated one of said input signals and has a value substantially equal to a previously occurring value of said one input signal;   means for comparing substantially current values of said input signals with the values of said digital signals and producing a control signal in response to at least one pre-defined logical difference, said difference occurring between one of said input signals and a corresponding one of said digital signals; and   means, responsive to said control signal and to the digital signals, for storing in parallel a set of simultaneously occurring values of all of said digital signals, wherein each value in said set is a current value of a different corresponding one of said digital signals. .Iaddend. .Iadd.16. The waveform recorder of claim 15 further comprising means, responsive to said control signal, for storing a "time-tag" value which represents a time at which the values of the digital signals that form said set simultaneously occurred. .Iaddend. .Iadd.17. The waveform recorder of claim 16 further comprising means, connected to said storing means, for accessing a desired set of the simultaneously occurring values of all the digital signals that have been stored within all of said data channels and routing each stored value in said accessed set to an associated output lead as part of a corresponding digital output signal. .Iaddend. .Iadd.18. The waveform recorder of claim 16 wherein each of said data channels comprises:   a memory;   1atch means, responsive to a corresponding one of said input signals and to said clock pulse, for providing the previously occurring value of said corresponding one input signal as a corresponding one of said digital signals;   means, responsive to said corresponding one of said input signals and to said corresponding one of said digital signals, for comparing the substantially current value of said corresponding one input signal to said previously occurring value thereof to detect a difference therebetween and for generating a first control signal whenever said difference is detected;   means, connected to said memory and responsive to a second control signal, for instructing the memory to store the previously occurring value of said corresponding one input signal therein; and wherein said waveform recorder further comprises:     a control circuit, responsive to the first control signal generated by any of said data channels, for producing said second control signal to all of said data channels so that each data channel will simultaneously store a corresponding different one of said simultaneously occurring values of said digital signals, whereby all of said data channels will collectively store a next successive set of most recent simultaneously occurring values   
     
     
        of all of the digital signals. .Iaddend. .Iadd.19.  The waveform recorder in claim 18, wherein each of said data channels further comprises means, connected to said comparing means, for selectably preventing said first control signal generated by said comparing and generating means situated within said data channel from reaching said control circuit. .Iaddend. .Iadd.20. The waveform recorder of claim 18 wherein said comparing and generating means in each of said data channels comprises a gate, responsive to said corresponding one of said input signals and to the corresponding digital signal, for comparing the values thereof and generating said first control signal. .Iaddend. .Iadd.21. The waveform recorder of claim 18 wherein said latch means further comprises first and second serially connected latches wherein an output of said first latch is connected to said memory and an output of said second latch is connected to said comparing and generating means, and said instructing means comprises: means for enabling said first latch to store a substantially current value of said corresponding one input signal for a clock interval as said previously occurring value of said corresponding one input signal; and   means for causing the previously occurring value of said corresponding one input signal to be stored in said second latch and said memory. .Iaddend.   
     
     
        .Iadd.22.  The waveform recorder of claim 18 wherein said "time-tag" value storing means is contained within said control circuit, and said control circuit further comprises: means for accessing a stored "time tag" value from said "time-tag" value storing means; and   means for counting the accessed "time-tag" value to substantially zero prior to causing each one of all of said data channels to access a corresponding value within the desired set of said stored digital signal values from the memory contained in each of said data channels. .Iaddend. .Iadd.23. The waveform recorder of claim 22 wherein said control circuit further comprises means, connected to each of said data channels, for generating an address at which a corresponding value of each one of said digital signal values in said desired set is stored within the memory in each of the data channels and for applying said address to the memory situated within each of said data channels. .Iaddend. .Iadd.24. The waveform recorder of claim 23 wherein said control circuit further comprises means, connected to each of said data channels, for providing a third control signal to each of said data channels to access the desired set of the values of the digital signals stored within all of said data channels; and wherein each of said data channels further comprises means, connected to the memory in said each data channel and responsive to said third signal, for causing all of the memories in all of the data channels to substantially simultaneously access said desired set of the values of the digital signals. .Iaddend. .Iadd.25. The waveform recorder of claim 24 further comprising means, connected to said control circuit, for selectively setting a rate at which a plurality of sets of simultaneously occurring values of the digital signals are accessed to a desired integral multiple or fraction of a rate at which these sets were stored. .Iaddend. .Iadd.26. The waveform recorder of claim 18 wherein said control circuit means further comprises:   a plurality of input/output ports; and   means connected to each of said data channels and to each of said ports for transferring information between any of said data channels and any of said   
     
     
        ports. .Iaddend. .Iadd.27.  The waveform recorder of claim 18 wherein each of the input signals is a one-bit digital signal. .Iaddend. .Iadd.28. The waveform recorder of claim 18 wherein an analog input signal is applied to a selected one of the data channels, and the selected one of said data channels further comprises an analog-to-digital converter for converting said analog input signal to a substantially equivalent multi-bit digital value and for providing said equivalent multi-bit digital value as an input signal to the latch means contained within said selected channel. .Iaddend. .Iadd.29. The waveform recorder of claim 28 wherein said selected one of said data channels further comprises means, responsive to the current value of said corresponding one input signal and the previously occurring value thereof, for specifying bits of both said corresponding one input signal and the corresponding previously occurring value thereof that are to be compared by said comparing means. .Iaddend.