Digital signal processor

Abstract

A digital signal processor comprises a bus structure including a program bus, data bus and data input/output bus, a program memory, a program controller, an internal data memory made up of a plurality of 2-port memories for storing block data, an arithmetic operator, a DMA controller for implementing block data input/output between the internal data memory and an external data memory in parallel to an internal operation by the arithmetic operator, an address generator for generating addresses for the internal operation and DMA transfer concurrently and in parallel to the internal operation, and parallel data input/output ports for implementing parallel data communication with an external device independently of input/output operations and in asynchronous fashion. The processor executes an intricate adaptive process algorism such as image signal processing at high speed and at high throughput.

What is claimed is: 
     
       1. A digital signal processor comprising: a bus structure including a program bus for instruction transfer, a data bus only for internal data transfer and a data input/output bus only for data input and output;   a program memory which is separated from data memories for storing a certain program;   a program controller connected to said program memory and to said program bus for reading out said program from said program memory and for executing instruction transfer, internal operation and data input/output in parallel fashion;   an internal data memory comprising a plurality of 2-port memories, connected selectively to said data bus and said data input/output bus, and adapted to store data in block units;   an arithmetic operator connected selectively to said data bus and said internal memory for executing internal operations including binomial operations;   a direct memory access (DMA) controller connected to said program controller and to said program bus and connecting said internal data memory with an external data memory through said data input/output bus to implement DMA transfer for block data in parallel to said internal operation;   an address generator which generates an address of said internal data memory for internal operation by said arithmetic operator and an address of said external data memory for DMA transfer by said DMA controller concurrently and in parallel to said internal operation, said address generator being connected to said program bus, said data bus and said internal data memory; and   parallel data input/output interface means which include a first-in first-out (FIFO) memory and which connect an external device to said data bus and said FIFO memory to implement parallel data communication with said external device independently of input/output operations and in asynchronous fashion.   
     
     
       2. A digital signal processor according to claim 1, wherein said arithmetic operator comprises a first arithmetic/logic unit which receives two input data and performs at least addition or subtraction in a single instruction cycle; a multiplier which receives said two input data simultaneously with said arithmetic/logic unit and performs multiplication in one instruction cycle; a pipeline register which selectively stores one of outputs from said multiplier and said first arithmetic/logic unit; a data exchanger which selectively exchanges said two input data with an output of said pipeline register at first and second outputs thereof; a barrel shifter which shifts one of the outputs of said data exchanger for an arbitrary number of bits right or left; a second arithmetic/logic unit which receives the output of said barrel shifter and another output of said data exchanger to perform at least addition or subtraction; and a working register which stores the output of said second arithmetic/logic unit. 
     
     
       3. A digital signal processor according to claim .Iadd.2.Iaddend., wherein said arithmetic operator comprises a circuit which splits data to said first and second arithmetic/logic units and multiplier by dividing said data into high-order n/2 bits and low-order n/2 bits, and performs arithmetic operations on the split sections independently. 
     
     
       4. A digital signal processor according to claim 1, wherein said program controller comprises a controller which stores in a memory having addresses of 2m (where m is an integer larger than or equal to one) a program branch destination address or a differential address between a current address and a branch destination address, obtains the program branch destination address, or differential address by addressing said memory using a bit pattern of arbitrary k bits in a 1-bit flag register in which test flag bits of 1 in number are stored (where 1 is an integer larger than or equal to one, and k is an integer smaller than or equal to 1 and m), and causes said program to branch to the indicated branch destination address. 
     
     
       5. A digital signal processor according to claim 1, wherein said address generator comprises an address generator including at least five systems of address generating units which generate a regular 2-dimensional address in logical sense by implementing modulo addition-subtraction or accumulation separately for addresses in the horizontal and vertical directions of a picture, and subsequently generate a 1-dimensional address of said internal data memory or external data memory through weighting addition for two addresses in the horizontal and vertical directions. .Iadd. 
     
     
       6.  A digital signal processor, comprising: a bus structure including a program bus for instruction transfer, a data bus for internal data transfer, and a data input/output bus for data input and output, said buses being separated from each other;   a program memory which stores instructions and which is connected to said program bus;   controller means for executing instruction transfer, internal operations and data input/output in parallel fashion;   an internal data memory having at least one input port and least one output port connected to said data bus and said data input/output bus so as to enable concurrent data reading and writing to and from said internal data memory via said data bus and said data input/output bus;   an arithmetic operator unit connected to said data bus and having at least two inputs and one outputs for executing internal operations; and   an address generator which concurrently generates at least three memory addresses associated with said internal operations in parallel with execution of internal operations by said arithmetic operator unit. .Iaddend. .Iadd.7. A digital signal processor, comprising:   a bus structure including a program bus for instruction transfer, a data bus for internal data transfer, and a data input/output bus for data input and output, said buses being separated from each other;   a program memory which stores instructions and which is connected to said program bus;   first controller means for executing instruction transfer, internal operations and data input/output in parallel fashion;   an internal data memory having at least one input port and least one output port connected to said data bus and said data input/output bus so as to enable concurrent data reading and writing to and from said internal data memory via said data bus and said data input/output bus;   second controller means for controlling data transfer between said internal data memory and an external memory on said data input/output bus in parallel with said internal operations;   an arithmetic operator unit connected to said data bus and having at least two inputs and one output for executing internal operations; and   an address generator which concurrently generates at least three memory addresses associated with said internal operations parallel with execution of internal operations by said arithmetic operator unit. .Iaddend.   
     
     
        .Iadd.    A digital signal processor, comprising: a bus structure having a program bus for instruction transfer, a data bus for internal data transfer and a data input/output bus for data input and output, said buses being separated from each other;   a program memory connected to said program bus for storing program instructions;   controller means for controlling parallel execution of instruction transfer, internal operation and data input/output;   an internal data memory having at least one input port and least one output port connected to said data bus and said data input/output bus and capable of concurrent data reading and writing to and from said buses;   an arithmetic operator unit having at least two inputs and one output connected to said data bus, for executing internal operations; and   an address generator for concurrently generating at least three memory addresses associated with said internal operations in parallel with execution of internal operations of said arithmetic operator unit.   
     
     
        .Iaddend. .Iadd.9.  A digital signal processor, comprising: a bus structure having a program bus for instruction transfer, a data bus for internal data transfer and a data input/output bus for data input and output, said buses being separated from each other;   a program memory connected to said program bus for storing program instructions;   first controller means for controlling parallel execution of instruction transfer, internal operation and data input/output;   an internal data memory having at least one input port and least one output port connected to said data bus and said data input/output bus and capable of concurrent data reading and writing to and from said buses;   an external data memory;   an arithmetic operator unit having at least two inputs and one output connected to said data bus, for executing internal operations in parallel;   second controller means for controlling data transfer between said internal data memory and said external data memory in parallel with said internal operations; and   an address generator for concurrently generating at least three memory addresses associated with said internal operations in conjunction parallel with execution of internal operations by said arithmetic operator unit. .Iaddend.