Graphics data processing apparatus having image operations with transparent color having selectable number of bits

Abstract

A graphics data processing apparatus having graphic image operations on two images. Two graphic images are formed into a single combined image based upon a predetermined combination of the multibit color codes representing corresponding pixels of the two images. A transparent color code is permitted for the first of the graphic images. The combination of a transparent color code from the first graphic image with any color code from the second graphic image yields the color code of the second graphic image. This innovation enables the use of color codes having selectable numbers of bits set by the number stored in a pixel size register. In particular the transparent color code, which is detected by a transparent color code detection device independent of the image operation, has a selectable number of bits set by the pixel size register in a manner like any other color code. This enables the same graphics data processing apparatus to be applicable to a wide variety of applications having images using differing lengths of color codes while preserving the transparency function.

I claim: 
     
       1. A graphics image processing apparatus comprising: a pixel size register for storing a number indicative of the number of bits per pixel;   a first image memory for storing a first array of pixels, each pixel represented by a data code having the number of bits indicated by said pixel size register, one of said data codes corresponding to a transparent data code;   a second image memory for storing a second array of pixels, each pixel represented by a data code; and   a transparent data code detector connected to said first image memory for detecting said transparent data code stored by a pixel in said first array; and   an array image operator connected to said first and second image memories and transparent data code detector for performing an image operation to generate a third array of pixels from said first and second array of pixels, each pixel of said third array represented by a combination of the data codes representing corresponding pixels of said first and second arrays of pixels, wherein, for each pixel of said first array containing said transparent data code, the corresponding pixel of said third array of pixels is represented by the data code of the corresponding pixel in said second array of pixels.   
     
     
       2. A graphics .[.data.]. .Iadd.image .Iaddend.processing apparatus as claimed in claim 1, wherein: said array image operator further stores said third array of pixels in said second image memory, each pixel of said third array of pixels replacing the corresponding pixel of said second array of pixels.   
     
     
       3. A graphics image processing apparatus as claimed in claim 1, wherein: said transparent data code is represented by a data .[.word.]. .Iadd.code .Iaddend.where all bits are "0's".   
     
     
       4. A graphics image processing apparatus as claimed in claim 1, wherein: said image operation is a logical combination of the individual bits of the data code of the pixel in said first array and the data code of the corresponding pixel in said second array.   
     
     
       5. A graphics image processing apparatus as claimed in claim 1, wherein: said image operation is an arithmetic combination .[.dependent upon.]. .Iadd.of .Iaddend.the numbers represented by the data code of the pixel in said first array and by the data code of the corresponding pixel in said second array.   
     
     
       6. A graphics image processing apparatus comprising: a pixel size register for storing a number indicative of the number of bits per pixel;   a memory including a data portion for storing a source image represented by a first array of pixels, each pixel represented by a data code having the number of bits indicated by said pixel size register, one of said data codes corresponding to a transparent data code, and including a display portion for storing a display image represented by a second array of pixels, each pixel represented by data code;   a transparent data code detector connected to said memory for detecting a transparent data code stored by a pixel of said source image; and   an array image operator connected to said memory and said transparent .[.color.]. .Iadd.data .Iaddend.code detector for performing an image operation to generate a third array of pixels, each pixel of said third array represented by a combination of the data codes representing corresponding pixels of said first and second arrays of pixels, wherein, for each pixel of said first array containing said transparent data code, the corresponding pixel of said third array of pixels is represented by the data code of the corresponding pixel in said second array of pixels.   
     
     
       7. A graphics image processing apparatus as claimed in claim 6, wherein: said array image operator further stores said third array of pixels in said display portion of said memory, each pixel of said third array of pixels replacing the corresponding pixel of said second array of pixels.   
     
     
       8. A graphics image processing apparatus as claimed in claim 6, wherein: said transparent data code is represented by a data .[.word.]. .Iadd.code .Iaddend.where all bits are "0's".   
     
     
       9. A graphics image processing apparatus as claimed in claim 6, wherein: said image operation is a logical combination of the individual bits of the data code of the pixel in said source image and the data code of the corresponding pixel in said display image.   
     
     
       10. A graphics image processing apparatus as claimed in claim 6, wherein: said image operation is an arithmetic combination of the numbers represented by the data code of the pixel in said source image and by the data code of the corresponding pixel in said display image. .Iadd.   
     
     
       11.  The graphics image processing apparatus of claim 1 in which said number of bits per pixel can vary. .Iaddend. .Iadd.12. The graphics image processing apparatus of claim 1 in which said number of bits per pixel can be 1, 2, 4, 8, or 16. .Iaddend. .Iadd.13. The graphics image processing apparatus of claim 1 in which said pixel size register has several bit locations and a bit in a certain location indicates said number of bits per pixel. .Iaddend. .Iadd.14. The graphics image processing apparatus of claim 1 in which said first and second image memories are formed in different locations of the same video random access memory. .Iaddend. .Iadd.15. The graphics image processing apparatus of claim 1 in which said first array is a source array and said second array is a destination array. .Iaddend. .Iadd.16. The graphics image processing apparatus of claim 1 in which said transparent data code is selectable. .Iaddend. .Iadd.17. The graphics image processing apparatus of claim 1 in which said transparent data code presents a number of bits that are all the same. .Iaddend. .Iadd.18. The graphics image processing apparatus of claim 1 in which said transparent data code detector indicates bit by bit said detection of said transparent data code. .Iaddend. .Iadd.19. The graphics image processing apparatus of claim 1 in which said array image operator includes pixel processing logic receiving said first and second arrays of pixels. .Iaddend. .Iadd.20. The graphics image processing apparatus of claim 19 in which said pixel processing logic forms an arithmetic combination on the individual pixel data from the first and second arrays of pixels. .Iaddend. .Iadd.21. The graphics image processing apparatus of claim 19 in which said pixel processing logic forms a logical combination on the individual pixel data from the first and second arrays of pixels. .Iaddend. .Iadd.22. The graphics image processing apparatus of claim 1 in which said array image operator includes transparency select logic connected to said transparent data code detector and coupled to said first and second arrays for generating said third array of pixels. .Iaddend. .Iadd.23. The graphics image processing apparatus of claim 22 in which said transparency select logic performs said generation of said third array on a bit by bit basis. .Iaddend. .Iadd.24. The graphics image processing apparatus of claim 23 in which said transparency select logic performs said generation by selecting bits from said first array and from a combination of said first and second arrays. .Iaddend. .Iadd.25. The graphics image processing apparatus of claim 6 in which said number of bits per pixel can vary. .Iaddend. .Iadd.26. The graphics image processing apparatus of claim 6 in which said number of bits per pixel can be 1, 2, 4, 8, or 16. .Iaddend. .Iadd.27. The graphics image processing apparatus of claim 6 in which said pixel size register has several bit locations and a bit in a certain location indicates said number of bits per pixel. .Iaddend. .Iadd.28. The graphics image processing apparatus of claim 6 in which said memory is a video random access memory and said data and display portions are formed in different locations of said video random access memory. .Iaddend. .Iadd.29. The graphics image processing apparatus of claim 6 in which said first array is a source and said second array is a destination array. .Iaddend. .Iadd.30. The graphics image processing apparatus of claim 6 in which said transparent data code is selectable. .Iaddend. .Iadd.31. The graphics image processing apparatus of claim 6 in which said transparent data code presents a number of bits that are all the same. .Iaddend. .Iadd.32. The graphics image processing apparatus of claim 6 in which said transparent data code detector indicates bit by bit said detection of said transparent data code. .Iaddend. .Iadd.33. The graphics image processing apparatus of claim 6 in which said array image operator includes pixel processing logic receiving said first and second arrays of pixels. .Iaddend. .Iadd.34. The graphics image processing apparatus of claim 33 in which said pixel processing logic forms an arithmetic combination on the individual pixel data from the first and second arrays of pixels. .Iaddend. .Iadd.35. The graphics image processing apparatus of claim 33 in which said pixel processing logic forms a logical combination on the individual pixel data from the first and second arrays of pixels. .Iaddend. .Iadd.36. The graphics image processing apparatus of claim 6 in which said array image operator includes transparency select logic connected to said transparent data code detector and coupled to said first and second arrays for generating said third array of pixels. .Iaddend. .Iadd.37. The graphics image processing apparatus of claim 36 in which said transparency select logic performs said generation of said third array on a bit by bit basis. .Iaddend. .Iadd.38. The graphics image processing apparatus of claim 37 in which said transparency select logic performs said generation by selecting bits from said first array and from 
     
     
        a combination of said first and second arrays. .Iaddend. .Iadd.39.  A graphics image processing apparatus comprising: a memory including a first data portion for storing a first image represented by a first array of pixels, each pixel represented by a data code, and including a second data portion for storing a second image represented by a second array of pixels, each pixel represented by a data code and at least one of said data codes corresponding to a transparency data code;   a transparency data code detector coupled to said memory for detecting said transparency data code; and   an array image operator coupled to said memory and connected to said transparency data code detector for performing an image operation to generate a third array of pixels, each pixel of said third array represented by data codes of a combined array of pixels formed by a combination of the data codes representing corresponding pixels of said first and second arrays and, for each pixel containing said transparency data code, the corresponding pixel of said third array of pixels is represented by the data code of the corresponding pixel of one of said   
     
     
        arrays of pixels other than said combined array. .Iaddend. .Iadd.40.  The graphics image processing apparatus of claim 39 in which said first array is a source array, said second array is a destination array, said transparency data code is contained in said first array and, for each pixel in said first array containing said transparency data code, each corresponding pixel of said third array of pixels is represented by the data code of the corresponding pixel of said second array of pixels. .Iaddend. .Iadd.41. The graphics image processing apparatus of claim 39 in which said array image operator further stores said third array of pixels in said second data portion of said memory. .Iaddend. .Iadd.42. The graphics image processing apparatus of claim 39 in which said array image operator further stores said third array of pixels in said second data portion of said memory, each pixel of said third array of pixels replacing the corresponding pixel of said second array of pixels. .Iaddend. .Iadd.43. The graphics image processing apparatus of claim 39 in which said transparency data code is represented by a data code where all bits are "0's". .Iaddend. .Iadd.44. The graphics image processing apparatus of claim 39 in which said image operation is a logical combination of the individual bits of the data code of the pixel in said first array and the data code of the corresponding pixel in said second array. .Iaddend. 
     
     
        .Iadd.5.  The graphics image processing apparatus of claim 39 in which said image operation is an arithmetic combination of the numbers represented by the data code of the pixel in said first array and by the data code of the corresponding pixel in said second array. .Iaddend. .Iadd.46. The graphics image processing apparatus of claim 39 in which said transparency data code detector indicates, on a bit by bit basis, a detection of said transparency data code. .Iaddend. .Iadd.47. The graphics image processing apparatus of claim 39 in which said array image operator includes pixel processing logic receiving said first and second arrays of pixels to form combined pixel data. .Iaddend. .Iadd.48. The graphics image processing apparatus of claim 39 in which said array image operator includes pixel processing logic receiving said first and second arrays of pixels to form combined pixel data, and transparency select logic receiving said second array of pixels and connected to said pixel processing logic and said transparent data code detector for generating said third array of pixels. .Iaddend. .Iadd.49. The graphics image processing apparatus of claim 48 in which said transparency select logic 
     
     
        generates said third array on a bit by bit basis. .Iaddend. .Iadd.50.  The graphics image processing apparatus of claim 48 in which said transparency select logic generates said third array of pixels by selecting bits from said combined pixel data and said second array of pixels. .Iaddend. 
     
     
        .Iadd. 1.  A graphics image processing apparatus comprising: a. memory circuits storing graphics data and program instruction, the graphics data including a first data portion for storing a first image represented by a first array of pixels, each pixel represented by a data code, and including a second data portion for storing a second image represented by a second array of pixels, each pixel represented by a data code and at least one of said data codes corresponding to a transparency data code; and   b. graphics processor circuits including: i. memory interface circuits connected to the memory circuits for accessing the graphics data and program instructions stored in the memory circuits;   ii. a central processing unit connected to the memory interface circuits for executing accessed program instructions to perform arithmetic and logic functions and graphics processing operations on the graphics data accessed by the memory interface circuits; and     iii. graphics circuits connected to the memory interface circuits and the central processing unit for operating in conjunction with and under control of the central processing unit to perform graphics processing operations, the graphics circuits including an image operator connected to the memory interface circuits for performing an image operation to generate a third array of pixels, each pixel of the third array represented by data codes of a combined array of pixels formed by a combination of the data codes representing corresponding pixels of the first and second arrays and, for each pixel containing the transparency data code, each corresponding pixel of the third array of pixels is represented by the data code of the corresponding pixel of one of the arrays of pixels other than the combined array of pixels. .Iaddend.   
     
     
        .Iadd. 2.  The graphics image processing apparatus of claim 51 in which said first array is a source array, said second array is a destination array, said transparency data code is contained in said first array and, for each pixel in said first array containing said transparency data code, each corresponding pixel of said third array of pixels is represented by the data code of the corresponding pixel of said second array of pixels. .Iaddend. .Iadd.53. The graphics image processing apparatus of claim 51 in which said array image operator further stores said third array of pixels in said second data portion of said memory. .Iaddend. .Iadd.54. The graphics image processing apparatus of claim 51 in which said array image operator further stores said third array of pixels in said second data portion of said memory, each pixel of said third array of pixels replacing the corresponding pixel of said second array of pixels. .Iaddend. .Iadd.55. The graphics image processing apparatus of claim 51 in which said transparency data code is represented by a data code where all bits are "0's". .Iaddend. .Iadd.56. The graphics image processing apparatus of claim 51 in which said image operation is a logical combination of the individual bits of the data code of the pixel in said first array and the data code of the corresponding pixel in said second array. .Iaddend. 
     
     
        .Iadd.7.  The graphics image processing apparatus of claim 51 in which said image operation is an arithmetic combination of the numbers represented by the data code of the pixel in said first array and by the data code of the corresponding pixel in said second array. .Iaddend. .Iadd.58. The graphics image processing apparatus of claim 51 in which said image operator indicates, on a bit by bit basis, a detection of said transparency data code. .Iaddend. .Iadd.59. The graphics image processing apparatus of claim 51 in which said image operator includes pixel processing logic receiving said first and second arrays of pixels to form combined pixel data. .Iaddend. .Iadd.60. The graphics image processing apparatus of claim 51 in which said array image operator includes pixel processing logic receiving said first and second arrays of pixels to form combined pixel data, and transparency select logic receiving said second array of pixels and connected to said pixel processing logic for generating said third array of pixels. .Iaddend. .Iadd.61. The graphics image processing apparatus of claim 60 in which said transparency select logic generates said third array on a bit by bit basis. .Iaddend. 
     
     
        .Iadd.     The graphics image processing apparatus of claim 60 in which said transparency select logic generates said third array of pixels by selecting bits from said combined pixel data and said second array of pixels. .Iaddend.