Method and circuitry for testing a programmable logic device

Abstract

A test configuration register (80) associated with a programmable memory device (88), wherein the signals at the outputs of the test configuration register force elements of the memory device into certain logic states to enable the device to be tested without programming the device's logic array (22).

What is claimed is: 
     
       1. Circuitry for synchronously or asynchronously testing the functions of a programmable logic device, said device including a plurality of elements responsive to logic signals and a plurality of input lines, said input lines forming a portion of a data flow path of said device when not in test mode, comprising: a test memory operable to receive, store and output a plurality of test configuration bits; and   circuitry responsive to said test configuration bits for forcing said elements of the logic device into pre-determined configurations while test signals are applied to at least one or said plurality of input lines.   
     
     
       2. The circuitry of claim 1 and further comprising a gate coupled to said memory and operable to output test configuration bits to said forcing circuitry responsive to a control signal applied to the logic device. 
     
     
       3. The circuitry or claim 1 wherein one of the elements comprises a true input buffer and wherein said forcing circuitry includes circuitry to disable the true input buffer of the logic device. 
     
     
       4. The circuitry of claim 1 wherein one of the elements comprises a false input buffer and wherein said forcing circuitry includes circuitry to disable the false input buffer of the logic device. 
     
     
       5. The circuitry of claim 1 wherein one of the elements comprises an output and wherein said forcing circuitry includes circuitry to enable the output of the logic device. 
     
     
       6. The circuitry of claim 1 wherein one of the elements comprises a sum-of-products term and wherein said forcing circuitry includes circuitry to force the logical state of the sum-of-product term of the logic device. 
     
     
       7. The circuitry of claim 1 wherein one of the elements comprises a feedback true buffer and wherein said forcing circuitry includes circuitry to disable the feedback true buffer of the logic device. 
     
     
       8. The circuitry of claim 1 wherein one of the elements comprises a feedback false buffer and wherein said forcing circuitry includes circuitry to disable the feedback false buffer of the logic device. 
     
     
       9. The circuitry of claim 1 wherein one of the elements comprises an input/output buffer and wherein said forcing circuitry includes circuitry to disable the input/output buffer of the logic device. 
     
     
       10. The circuitry of claim 1 wherein one of the elements comprises a polarity switch and wherein said forcing circuitry includes circuitry to set and clear the polarity switch of the logic device. 
     
     
       11. The circuitry of claim 1 wherein one of the elements comprises a registered/combinatorial switch and wherein said forcing circuitry includes circuitry to select registered and combinatorial output of the logic device. 
     
     
       12. The circuitry of claim 1 wherein one of the elements comprises an asynchronous reset product term and wherein said forcing circuitry includes circuitry to disable the asynchronous reset product term of the logic device. 
     
     
       13. The circuitry of claim 1 wherein one of the elements comprises a synchronous preset product term and wherein said forcing circuitry includes circuitry to disable the synchronous preset product term of the logic device. 
     
     
       14. A method for synchronously or asynchronously testing the functions of a programmable logic device, comprising the steps of: loading a test memory with test configuration bits;   forcing a configuration of the logic device responsive to the signals at the outputs of said test memory; and   applying a test signal to at least one input line of said device, wherein said input line forms a portion of a data flow path of said device when not in test mode.   
     
     
       15. The method of claim 14 and further comprising the step of applying an enabling signal to the test memory. 
     
     
       16. The method of claim 14 wherein said loading step comprises the step of serially inputting the test configuration bits into the test memory. 
     
     
       17. The method of claim 14 wherein said forcing step comprises the steps of: latching the test configuration bits in the memory;   gating the test configuration bits at the outputs of the memory with a test gating signal; and   applying the test configuration bits from the outputs of the memory to elements of the logic device.   
     
     
       18. The method of claim 17 wherein said applying step comprises the steps of: forcing elements of the logic device into logic conditions determined by the test configuration bits; and   testing the functionality and performance of the resulting logical configuration.   
     
     
       19. The method of claim 18 wherein said testing step further comprises the steps of testing the sum-of-products terms of the logic device. 
     
     
       20. The method of claim 18 wherein said testing step comprises the step of measuring T pd  from every input terminal of the logic device to every input/output terminal of the logic device. 
     
     
       21. The method of claim 18 wherein said testing step comprises the step of measuring T su  and T co  for every output of the logic device. 
     
     
       22. The method of claim 18 wherein said testing step comprises the step of measuring T su  from every input terminal of the logic device to every input/output terminal of the logic device. 
     
     
       23. The method of claim 18 wherein said testing step comprises the step of measuring T en  and T dis  from every input terminal of the logic device to every input/output terminal of the logic device. 
     
     
       24. The method of claim 18 wherein said testing step comprises the step of measuring T en  and T dis  for every input/output terminal of the logic device to every other input/output terminal of the logic device. 
     
     
       25. The method of claim 18 wherein said testing step comprises the step of measuring T pd  for asynchronous reset from every input terminal of the logic device to every input/output terminal of the logic device. 
     
     
       26. The method of claim 18 wherein said testing step comprises the step of measuring T su  for synchronous preset from every input terminal of the logic device to every input/output terminal of the logic device. 
     
     
       27. A programmable logic device comprising: a plurality of elements responsive to logic signals;   a plurality of input lines operable for inputting logic signals to said device, said plurality of input lines further operable for inputting test signals to said device, wherein said input lines form a portion of a data flow path of said device when not in test mode;   a test memory operable to receive, store and output said test configuration bits; and   circuitry responsive to said test configuration bits for forcing said elements of the logic device into predetermined configurations while said test signals are applied to said plurality of input lines.   
     
     
       28. The programmable logic device of claim 27 and further comprising a gate coupled to said test memory and operable to output test configuration bits to said configuring circuitry responsive to a control signal applied to the logic device. 
     
     
       29. The programmable logic device of claim 27 wherein one of the elements comprises a true input buffer and wherein said configuring circuitry includes circuitry to disable the true input buffer of the programmable logic device. 
     
     
       30. The programmable logic device of claim 27 wherein one of the elements comprises a false input buffer and wherein said configuring circuitry includes circuitry to disable the false input buffer of the programmable logic device. 
     
     
       31. The programmable logic device of claim 27 wherein one of the elements comprises an output and wherein said configuring circuitry includes circuitry to disable the output of the programmable logic device. 
     
     
       32. The programmable logic device of claim 27 wherein one of the elements comprises a sum-of-products term and wherein said configuring circuitry includes circuitry to force the logical state of the sum-of-products term of the programmable logic device. 
     
     
       33. The programmable logic device of claim 27 wherein one of the elements comprises feedback true buffer and wherein said configuring circuitry includes circuitry to disable the feedback true buffer of the programmable logic device. 
     
     
       34. The programmable logic device of claim 27 wherein one of the elements comprises feedback false buffer and wherein said configuring circuitry includes circuitry to disable the feedback false buffer of the programmable logic device. 
     
     
       35. The programmable logic device of claim 27 wherein one of the elements comprises an input/output buffer and wherein said configuring circuitry includes circuitry to disable the input/output buffer of the programmable logic device. 
     
     
       36. The programmable logic device of claim 27 wherein one of the elements comprises a polarity switch and wherein said configuring circuitry includes circuitry to disable the polarity switch of the programmable logic device. 
     
     
       37. The programmable logic device of claim 27 wherein one of the elements comprises a registered/combinatorial switch and wherein said configuring circuitry includes circuitry to force the state of the registered/combinatorial switch of the programmable logic device. 
     
     
       38. The programmable logic device of claim 27 wherein one of the elements comprises an asynchronous reset product term and wherein said configuring circuitry includes circuitry to disable the asynchronous reset product term of the programmable logic device. 
     
     
       39. The programmable logic device of claim 27 wherein one of the elements comprises a synchronous preset product term and wherein said configuring circuitry includes circuitry to disable the synchronous reset product term of the programmable logic device. .Iadd. 
     
     
       40.  Circuitry for synchronously or asynchronously testing the functions of a device including a plurality of elements responsive to logic signals and a plurality of input lines, the input lines forming a portion of a data flow path of the device when not in test mode, comprising: a test memory operable to receive, store and output a plurality of test configuration bits; and   circuitry responsive to said test configuration bits for forcing the elements of the device into pre-determined configurations while test signals are applied to at least one of the plurality of input lines. .Iaddend. .Iadd.   
     
     
       41.  The circuitry of claim 40 and further comprising a gate coupled to said memory and operable to output test configuration bits to said forcing circuitry responsive to a control signal applied to the device. .Iaddend. .Iadd.42. The circuitry of claim 40 wherein one of the elements comprising a true input buffer and wherein said forcing circuitry includes circuitry to disable the true input buffer of the device. .Iaddend. .Iadd.43. The circuitry of claim 40 wherein one of the elements comprises a false input buffer and wherein said forcing circuitry includes circuitry to disable the false input buffer of the device. .Iaddend. .Iadd.44. The circuitry of claim 40 wherein one of the elements comprises an output and wherein said forcing circuitry includes circuitry to enable the output of the device. .Iaddend. .Iadd.45. The circuitry of claim 40 wherein one of the elements comprises a sum-of-products term and wherein said forcing circuitry includes circuitry to force the logical state of the sum-of-product term of the device. .Iaddend. .Iadd.46. The circuitry of claim 40 wherein one of the elements comprises a feedback true buffer and wherein said forcing circuitry includes circuitry to disable the feedback true buffer of the 
     
     
        device. .Iaddend. .Iadd.47.  The circuitry of claim 40 wherein one of the elements comprises a feedback false buffer and wherein said forcing circuitry includes circuitry to disable the feedback false buffer of the device. .Iaddend. .Iadd.48. The circuitry of claim 40 wherein one of the elements comprises an input/output buffer and wherein said forcing circuitry includes circuitry to disable the input/output buffer of the device. .Iaddend. .Iadd.49. The circuitry of claim 40 wherein one of the elements comprises a polarity switch and wherein said forcing circuitry includes circuitry to set and clear the polarity switch of the device. .Iaddend. .Iadd.50. The circuitry of claim 40 wherein one of the elements comprises a registered/combinatorial switch and wherein said forcing circuitry includes circuitry to select registered and combinatorial output of the device. .Iaddend. .Iadd.51. The circuitry of claim 40 wherein one of the elements comprises an asynchronous reset product term and wherein said forcing circuitry includes circuitry to disable the asynchronous reset product term of the device. .Iaddend. .Iadd.52. The circuitry of claim 40 wherein one of the elements comprises a synchronous preset product term and wherein said forcing circuitry includes circuitry to disable the synchronous preset product term of the device. .Iaddend. .Iadd.53. A method for synchronously or asynchronously testing the functions of a device, comprising the steps of: loading a test memory with test configuration bits;   forcing a configuration of the device responsive to signals output from the test memory; and   applying a test signal to at least one input line of the device, wherein the input line forms a portion of a data flow path of the device when not in test mode. .Iaddend. .Iadd.54. The method of claim 53 and further comprising the step of applying an enabling signal to the test memory. .Iaddend. .Iadd.55. The method of claim 53 wherein said loading step comprises the step of serially inputting the test configuration bits into   
     
     
        the test memory. .Iaddend. .Iadd.56.  The method of claim 53 wherein said forcing step comprises the steps of: latching the test configuration bits in the memory;   gating the test configuration bits at the outputs of the memory with a test gating signal; and   applying the test configuration bits from the outputs of the memory to elements of the device. .Iaddend. .Iadd.57. The method of claim 56 wherein said applying step comprises the steps of:   forcing elements of the device into logic conditions determined by the test configuration bits; and   testing the functionality and performance of the resulting logical configuration. .Iaddend. .Iadd.58. The method of claim 57 wherein said testing step further comprises the steps of testing the sum-of-products terms of the device. .Iaddend. .Iadd.59. The method of claim 57 wherein said testing step comprises the step of measuring T pd  from every input terminal of the device to every input/output terminal of the device. .Iaddend. .Iadd.60. The method of claim 57 wherein said testing step comprises the step of measuring T su  and T co  for every output of the device. .Iaddend. .Iadd.61. The method of claim 57 wherein said testing step comprises the step of measuring T su  from every input terminal of the device to every input/output terminal of the device. .Iaddend. .Iadd.62. The method of claim 57 wherein said testing step comprises the step of measuring T en  and T dis  from every input terminal of the device to every input/output terminal of the device.   
     
     
        .Iaddend. .Iadd.63.  The method of claim 57 wherein said testing step comprises the step of measuring T en  and T dis  for every input/output terminal of the device to every other input/output terminal of the device. .Iaddend. .Iadd.64. The method of claim 57 wherein said testing step comprises the step of measuring T pd  for asynchronous reset from every input terminal of the device to every input/output terminal of the device. .Iaddend. .Iadd.65. The method of claim 57 wherein said testing step comprises the step of measuring T su  for synchronous preset from every input terminal of the device to every input/output terminal of the device. .Iaddend. .Iadd.66. A device, comprising: a plurality of elements responsive to logic signals;   a plurality of input lines operable for inputting logic signals to the device, said plurality of input lines further operable for inputting test signals to the device, wherein said input lines form a portion of a data flow path of the device when no in test mode;   a test memory operable to receive, store and output a plurality of test configuration bits; and   circuitry responsive to said test configuration bits for forcing said elements of the device into pre-determined configurations while said test signals are applied to said plurality of input lines. .Iaddend. .Iadd.67. The device of claim 66 and further comprising a gate coupled to said test memory and operable to output test configuration bits to said configuring circuitry responsive to a control signal applied to the device. .Iaddend. .Iadd.68. The device of claim 66 wherein one of the elements comprises a true input buffer and wherein said configuring circuitry includes circuitry to disable the true input buffer of the device. .Iaddend. .Iadd.69. The device of claim 66 wherein one of the elements comprises a false input buffer and wherein said configuring circuitry includes circuitry to disable the false input buffer of the device. .Iaddend. .Iadd.70. The device of claim 66 wherein one of the elements comprises an output and wherein said configuring circuitry includes circuitry to   
     
     
        disable the output of the device. .Iaddend. .Iadd.71.  The device of claim 66 wherein one of the elements comprises a sum-of-products term and wherein said configuring circuitry includes circuitry to force the logical state of the sum-of-products term of the device. .Iaddend. .Iadd.72. The device of claim 66 wherein one of the elements comprises feedback true buffer and wherein said configuring circuitry includes circuitry to disable the feedback true buffer of the device. .Iaddend. .Iadd.73. The device of claim 66 wherein one of the elements comprises feedback false buffer and wherein said configuring circuitry includes circuitry to disable the feedback false buffer of the device. .Iaddend. .Iadd.74. The device of claim 66 wherein one of the elements comprises an input/output buffer and wherein said configuring circuitry includes circuitry to disable the input/output buffer of the device. .Iaddend. .Iadd.75. The device of claim 66 wherein one of the elements comprises a polarity switch and wherein said configuring circuitry includes a circuitry to disable the polarity switch of the device. .Iaddend. .Iadd.76. The device of claim 66 wherein one of the elements comprises a registered/combinatorial switch and wherein said configuring circuitry includes circuitry to force the state of the registered/combinatorial switch of the device. .Iaddend. .Iadd.77. The device of claim 66 wherein one of the elements comprises an asynchronous reset product term and wherein said configuring circuitry includes circuitry to disable the asynchronous reset product term of the 
     
     
        device. .Iaddend. .Iadd.78.  The device of claim 66 wherein one of the elements comprises a synchronous preset product term and wherein said configuring circuitry includes circuitry to disable the synchronous reset product term of the device. .Iaddend.