Bit line and column circuitry used in a semiconductor memory

Abstract

Column circuitry for a CMOS static RAM includes a bit line clamp combined with a bit line current source regulated by a voltage reference which tracks changes in transistor characteristics. Separate data read and data write lines are provided, with a differential amplifier for each pair of bit lines. The data read lines are coupled to compensated current source loads, and the differential amplifiers are couplled to switching transistors which are also compensated for transistor characteristic changes, Each bit line pair has a sneak capacitance prevention transistor so that in non-selected columns the bit line pairs are coupled together allowing the memory cells therein to pull down all of the bit lines. This isolates the read lines from unwanted capacitance in the differential amplifiers of each of the non-selected columns, Further, a VCC protection circuit is provided.

I claim: 
     
       1. In a CMOS integrated circuit device, a memory array and control circuitry therefor comprising: a plurality of pairs of column lines;   a plurality of word lines;   a plurality of multi-transistor memory cells, each cell including a pair of cross-coupled N-channel transistors and being located at an intersection of, and connected to, a pair of column lines and one said word line;   a plurality of bias .[.means.]. .Iadd.circuite .Iaddend.each connected to a corresponding column line, each .[.said.]. bias .Iadd.circuit .Iaddend..].means.]. including a P-channel transistor and an N-channel transistor each having its source-drain path coupled between a supply voltage and .[.said.]. .Iadd.a .Iaddend.corresponding column line, each .[.said.]. bias .[.means serving to limit the current drain to the threshold level of said P-channel transistor.]. .Iadd.circuit being arranged to limit the voltage swing on the corresponding column line .Iaddend.as the .Iadd.corresponding .Iaddend.column line for the particular bias .[.means.]. .Iadd.circuit .Iaddend.is pulled toward ground; and   a voltage reference circuit .[.connected.]. .Iadd.coupled .Iaddend.to said supply voltage .[.input.]. and having an output connected to the gates of said P-channel transistors for each pair of .[.said.]. bias .[.means.]. .Iadd.circuits .Iaddend.connected to a pair of column lines, said reference circuit providing compensation means for reducing the effects of .[.process variations between elements of said.]. .Iadd.changes in the ambient conditions within the integrated circuit .Iaddend.device.   
     
     
       2. The integrated circuit device of claim 1 wherein each said memory cell is a cross-coupled latch circuit comprised of four N-channel transistors. 
     
     
       3. The circuit of claim 1 wherein said voltage reference circuit includes a self-biased inverter including a P-channel transistor and an N-channel transistor. 
     
     
       4. In a CMOS integrated circuit device, a memory array and control circuitry therefor comprising: a plurality of pairs of column lines, each pair constituting a bit line and a bit bar line;   a plurality of work lines extending transverse to said pairs of column lines;   a plurality of multi-transistor memory cells, each cell being located at an intersection of, and connected to, one word line and one pair of columns lines;   a plurality of bias .[.means.]. .Iadd.circuits .Iaddend., each connected to one end of a corresponding column line, each .[.said.]. bias .[.means.]. .Iadd.circuit .Iaddend.including a P-channel transistor and an N-channel transistor, each .Iadd.of said transistors .Iaddend.having its source-drain path connected between a supply voltage and .[.the.]. .Iadd.a .Iaddend.corresponding column line, each .[.said.]. bias .[.means being operative for limiting the current drain to the threshold level of said P-channel transistor.]. .Iadd.circuit being arranged to limit the voltage swing on the corresponding column line .Iaddend.as the corresponding column line for the particular bias .[.means.]. .Iadd.circuit .Iaddend.is pulled toward ground; and   a voltage reference circuit having an output connected to the gates of the P-channel transistors for the bias .[.means.]. .Iadd.circuits .Iaddend.for .[.column line pairs.]. .Iadd.said pairs of column lines .Iaddend., said reference circuit having transistor elements sized to mirror transistor elements of said bias .[.means.]. .Iadd.circuits .Iaddend.and said memory cells and thereby compensate for .[.process variation within said.]. .Iadd.changes in the ambient conditions within the integrated circuit .Iaddend.device.   
     
     
       5. The circuit device according to claim 4 wherein said voltage reference circuit is comprised of a first P-channel transistor having its drain connected to .Iadd.a .Iaddend.first .[.a.]. source voltage and three N-channel transistors having their source drain paths coupled in series between the source of said first P-channel transistor and a reference potential. 
     
     
       6. The column circuitry according to claim 4 wherein said voltage reference circuit includes P-channel transistors and N-channel transistors to provide a first reference voltage which varies to compensate for changes in the ambient conditions within the semi-conductor memory. 
     
     
       7. In a semi-conductor memory having at least two columns of memory cells for storing data, each column having a pair of bit lines coupled to plurality of memory cells, said memory having a pair of data read lines and having address means for providing a column select signal to each column, column circuitry comprising: a respective differential amplifier for each of said columns, each said differential amplifier being coupled between said read lines and the pair of bit lines in the corresponding column, each differential amplifier being responsive to an associated column select signal to provide output signals on the read lines representative of the data stored in one of the memory cells in the corresponding columns when the column is selected; and   Sneak capacitance reduction means coupled between the pair of bit lines in each of columns and responsive to a column select signal for coupling together the pair of bit lines in a corresponding column when the corresponding column is not selected.   
     
     
       8. The column circuity according to claim 7 wherein said sneak capacitance reduction means includes, for each column, a transistor having its source/drain path coupled between the bit lines in the corresponding column and having its gate coupled to a select signal. 
     
     
       9. In a CMOS integrated circuit device, a memory array and control circuitry therefor comprising: a plurality of pairs of bit lines;   a plurality of word lines extending transverse to said pairs of bit lines;   a plurality of multi-transistor memory cells, each cell including a pair of cross-coupled transistors and being located at an intersection of, and connected to, a corresponding pair of bit lines and a corrsponding word line;   a plurality of bias circuits coupled to said bit lines, each one of said bit lines corresponding to a respective bias circuit, each .[.said.]. bias circuit including a P-channel transistor and .Iadd.an .Iaddend.N-channel transistor coupled to each other and coupled between a supply voltage and the corresponding bit line, .[.said.]. .Iadd.each .Iaddend.bias circuit providing a clamp and a current source for the bit line corresponding to .[.the.]. .Iadd.that .Iaddend.bias circuit; and   a voltage reference circuit coupled to said supply voltage and having an output coupled to the gate electrodes of said P-channel transistors in said plurality of bias circuits, said reference circuit reducing the effects of .[.process variations between elements of said.]. .Iadd.changes in the ambient conditions within the integrateed circuit .Iaddend.device.   
     
     
       10. The integrated circuit device of claim 9 wherein each said memory cell comprises a cross-coupled latch circuit having four N-channel transistors. 
     
     
       11. The integrated circuit device of claim 9, said reference circuit having elements sized to track .[.the.]. effects .[.of.]. .Iadd.on .Iaddend.transistor elements of the plurality of bias circuits and said memory cells and thereby compensate for .[.process variations within said.]. .Iadd.changes in the ambient conditions within the integrated circuit.Iaddend.device. 
     
     
       12. The circuit device according to claim 9 wherein said voltage reference circuit comprises a first P-channel transistor having its source-drain coupled between a first source voltage and said output of said voltage reference circuit, and further comprises three N-channel transistors having their source-drain paths coupled in series between a reference potential and said ouptut. 
     
     
       13. The circuit of claim 9 wherein said voltage reference circuit includes a self-biased inverter including a P-channel transistor and an N-channel transistor. 
     
     
       14. The column circuitry of claim 9 wherein said voltage reference circuit provides a non-zero voltage to the gate electrodes of said P-channel transistors in said plurality of bias circuits. 
     
     
       15. The column circuitry of claim 9 wherein said semi-conductor memory includes a pair of data read lines coupled to a plurality of pairs of input transistors each gated by a corresponding bit line and each selectively coupling a respective data read line to a common node between an associated pair of input transistors, whereby each column comprises a pair of bit lines and has associated with it a respective common node selectively coupled to the data read lines; the column circuitry further comprising a current source load coupled to said data read lines and to a second voltage reference circuit which provides a second reference voltage which varies to compensate for changes in the ambient conditions within the semi-conductor memory. 
     
     
       16. The memory according to claim 15 further comprising a plurality of sneak capacitance reduction means each coupled between a respective pair of said bit lines and being responsive to a column select signal to couple the bit line pair together to permit the memory cell therebetween to isolate said read lines from each of said common nodes except for the common node in the selected column.