Monolithic integrated circuit having common external terminal for analog and digital signals and digital system using the same

Abstract

Herein disclosed is a digital semiconductor integrated circuit which is equipped with: a digital signal input circuit; an analog signal input circuit made receptive of an analog signal for feeing out a digital signal corresponding to said analog signal; and a common external terminal connected commonly with the input terminals of said digital signal input circuit and said analog signal input circuit. By the preparation with the use of a suitable switch circuit, the aforementioned common external terminal can be used as either an analog signal input terminal or a digital signal input terminal. As a result, the number of the external output terminals required for the aforementioned semiconductor integrated circuit can be reduced.

What is claimed is: 
     
       1. A microprocessor having a register, an internal bus, an arithmetic and logic unit, a plurality of external terminals and a control circuit, said microprocessor comprising: a digital .Iadd.signal .Iaddend.input circuit having at least one digital signal input node coupled to one or more of said plurality of external terminals and at least one output node;   an analog signal input circuit having at least one analog signal input node and at least one output node coupled to said internal bus;   first switching means for transmitting to said analog signal input node an analog signal from at least one of said external terminals coupled to said digital signal input circuit;   second switching means for selectively coupling said output node of said digital signal input circuit to said internal bus, and   address decoder means coupled to said first and second switching means and responsive to address signals for selectively activating one of said first and second switching means.   
     
     
       2. A microprocessor according to claim 1 wherein said analog signal input circuit comprises a converter for converting an analog signal on said analog signal input node to a digital signal. 
     
     
       3. A microprocessor according to claim 2 wherein said analog signal input circuit further comprises a register to be coupled to an output node of said converter. 
     
     
       4. A microprocessor according to claims 2 or 3 wherein said digital signal input circuit includes a register coupled to said second switching means. 
     
     
       5. In a digital control system having a controllable device having its operation controlled by digital control signals and a microprocessor receptive of both an analog signal and a digital signal for generating said digital control signals, the improvement comprising: a microprocessor having a register, an internal bus, an arithmetic and logic unit, a control circuit and a plurality of external terminals;   a digital signal input circuit having at least one digital signal input node coupled to one or more of said plurality of external terminals and at least one output node;   an analog signal input circuit having at least one analog signal input node coupled to one or more of said plurality of external terminals and at least one output node;   at least one of said external terminals being coupled commonly with the analog signal input node of said analog signal input circuit and the digital signal input node of said digital signal input circuit;   first switching means for coupling the output node of said digital signal input circuit to said internal bus;   second switching means for coupling the output node of said analog signal input circuit to said internal bus; and   . .wherein.!. .Iadd.address decoder means coupled to receive an address signal and for controlling said first and second switching means so that .Iaddend.each of said first and second switching means does not couple output nodes of said digital and said analog signal input circuits to said internal bus at the same time.   
     
     
       6. A digital control system according to claim 5 wherein said analog signal input circuit comprises a converter for converting an analog signal over said analog signal input node to digital signal. 
     
     
       7. In a microprocessor having a register, an internal bus, an arithmetic and logic unit, a control circuit and a plurality of external terminals, said microprocessor comprising: a digital signal input circuit having at least one digital signal input node coupled to one or more of said plurality of external terminals and at least one output node;   an analog signal input circuit having at least one analog signal input node coupled to one or more of said plurality of external terminals and at least one output node;   at least one of said external terminals being coupled commonly with the analog signal input node of said analog signal input circuit and the digital signal input node of said digital signal input circuit;   first switching means for coupling the output node of said digital signal input circuit to said internal bus;   second switching means for coupling the output node of said analog signal input circuit to said internal bus; and   . .wherein.!. .Iadd.address decoder means coupled to receive an address signal and for controlling said first and second switching means so that .Iaddend.each of said first and second switching means does not couple output nodes of said digital and said analog signal input circuits to said internal bus at the same time.   
     
     
       8. A microprocessor according to claim 7 wherein said analog signal input circuit comprises a converter for converting an analog signal over said analog signal input node to a digital signal. 
     
     
       9. A microprocessor according to claim 8 wherein said analog signal input circuit has a plurality of analog signal input nodes, and an analog multiplexer for transmitting one of analog input signals to be fed to said at least one analog signal input node to said converter. 
     
     
       10. A microprocessor . .acocrding.!. .Iadd.according .Iaddend.to claim 9 wherein said analog input circuit comprises a register to be coupled to an output node of said converter. 
     
     
       11. A microprocessor according to claims 8, 9 or 10 wherein said digital input circuit includes a register coupled to said first switching means. 
     
     
       12. In a microprocessor having a register, an internal bus, an arithmetic and logic unit, a control unit and a plurality of external terminals, said microprocessor comprising: a digital signal input output circuit having at least one digital signal input output node coupled to one or more of said plurality of external terminals and at least one output node;   an analog signal input circuit having at least one analog signal input node coupled to one or more of said plurality of external terminals and at least one output node;   at least one of said external terminals being coupled commonly with the analog signal input node of said analog signal input circuit and the digital signal input output node of said digital signal input output circuit;   first switching means for coupling the output node of said digital signal input output circuit to said internal bus;   second switching means for coupling the output node of said analog signal input circuit to said internal bus; and   . .wherein.!. .Iadd.an address decoder circuit coupled to receive an address signal and for controlling said first and second switching means so that .Iaddend.each of said first and second switching means does not couple output nodes of said digital signal input output circuit and said analog signal input circuits to said internal bus at the same time.   
     
     
       13. A microprocessor according to claim 12 wherein said analog signal input circuit comprises a converter for converting an analog signal over said analog signal input node to a digital signal. 
     
     
       14. A microprocessor according to claim 13 wherein said analog signal input circuit has a plurality of analog signal input nodes, and an analog multiplexer for transmitting one of analog input signals to be fed to said analog signal input nodes of said converter. 
     
     
       15. A microprocessor according to claim 14 wherein said analog input circuit comprises a register to be coupled to an output node of said converter. 
     
     
       16. A microprocessor according to claim 13, 14 or 15 wherein said digital input output circuit includes a register coupled to said first switching means. 
     
     
       17. In a digital control system having a controllable device having its operation controlled by digital control signals; and a microprocessor receptive of both an analog signal and a digital signal for generating said digital control signals, the improvement comprising: a microprocessor having a register, an internal bus, an arithmetic and logic unit, a control circuit and a plurality of external terminals;   a digital signal input output circuit having at least one digital signal input output node coupled to one or more of said plurality of external terminals and at least one output node;   an analog signal input circuit having at least one analog signal input node coupled to one or more of said plurality of external terminals and at least one output node;   at least one of said external terminals being coupled commonly with the analog signal input node of said analog signal input circuit and the digital signal input output node of said digital signal input output circuit;   first switching means for coupling the output node of said digital signal input output circuit to said internal bus;   second switching means for coupling the output node of said analog signal input circuit to said internal bus; and   . .wherein.!. .Iadd.an address decoder circuit responsive to an address signal and for controlling said first and second switching means so that .Iaddend.each of said first and second switching means does not couple output nodes of said digital signal input output circuit and said analog signal input circuits to said internal bus at the same time.   
     
     
       18. A digital control system according to claim 17 wherein said analog signal input circuit comprises a converter for converting an analog signal over said analog signal input node to digital signal. 
     
     
       19. A microprocessor having a register, an internal bus, an arithmetic and logic unit, a plurality of external terminals . .and control means,.!. said microprocessor comprising: a digital signal input circuit having at least one digital signal input node coupled to one or more of said plurality of external terminals;   an analog signal input circuit having at least one analog signal input node coupled to one or more of said plurality of external terminals;   at least one of said external terminals being coupled in common to said analog and said digital signal input circuits;   said digital signal input circuit having first switching means for selectively coupled said digital signal input node to said internal bus;   said analog signal input circuit having second switching means for selectively coupling said analog signal input node to said internal bus; and   .Iadd.address decoder means coupled to receive an address signal and for controlling .Iaddend.the switching states of said first and second switching means . .being controlled by said control means.!..   
     
     
       20. A microprocessor according to claim 19 wherein said analog signal input circuit comprises a converter for converting an analog signal over said analog signal input node to a digital signal. 
     
     
       21. A microprocessor according to claim 20 wherein said analog signal input circuit has a plurality of analog signal input nodes, and an analog multiplexer for transmitting one of analog input signals to be fed to said analog signal input nodes to said converter. 
     
     
       22. A microprocessor according to claim 21 wherein said analog signal input circuit comprises a register to be coupled to an output node of said converter. 
     
     
       23. In a digital control system having a controllable device having its operation controlled by digital control signals and a microprocessor receptive of both an analog signal and a digital signal for generating said digital control signals, the improvement comprising: a microprocessor having a register, an internal bus, an arithmetic and logic unit, an address decoder circuit coupled to receive an address signal and a plurality of external terminals;   a digital signal input circuit having at least one digital signal node coupled to one or more of said plurality of external terminals;   an analog signal input circuit having at least one analog signal input node coupled to one or more of said plurality of external terminals;   at least one of said external terminals being coupled in common to said analog and said digital signal input circuits;   said digital signal input circuit has first switching means for selectively coupling said digital signal input node to said internal bus;   said analog signal input circuit . .bus.!. .Iadd.has .Iaddend.second switching means for selectively coupling said analog signal input node to said internal bus; and   the switching states of said first and second switching means being controlled by said address decoder circuit.   
     
     
       24. A digital control system according to claim 23 wherein said analog signal input circuits comprises a converter for converting an analog signal over said analog signal input node to digital signal. 
     
     
       25. A . .microprocessor.!. .Iadd.digital control system .Iaddend.according to claim 24 wherein said analog signal input circuit has a plurality of analog signal input nodes, and an analog multiplexer for transmitting one of analog input signals to be fed to said analog signal input nodes to said converter. 
     
     
       26. A . .microcomputer.!. .Iadd.digital control system .Iaddend.according to claim 25 wherein said analog input circuit comprises a register to be coupled to an output node of said converter. .Iadd. 
     
     
       27.  A one-chip monolithic semiconductor integrated circuit including a microprocessor, RAM and ROM, the microprocessor including an internal data bus having data lines, an arithmetic and logic unit, and a plurality of external terminals, said microprocessor further comprising: a digital signal input circuit having first output lines and having a plurality of digital signal first input lines respectively coupled to said plurality of external terminals;   an analog signal input circuit having an analog signal input line coupled to one of said plurality of external terminals in common with one of said digital signal first input lines;   said first output lines of said digital signal input circuit being respectively coupled to at least some of the data lines of said internal data bus;   said digital signal input circuit having digital signal storage means for storing digital signals received from said external terminals prior to said digital signals being placed on said data lines of said internal data bus;   switches between said digital signal storage means and said internal data bus, and being selectively activated by first switching signals applied to said switches; and   address decoder means connected to said switches for decoding address signals and producing the first selecting signals for selectively activating and deactivating said switches according to the address signals..Iaddend. .Iadd.   
     
     
       28.  A one-chip monolithic semiconductor integrated circuit according to claim 27, wherein said digital signal storage means is a register; and further including an input buffer between said external terminals and said digital signal storage means..Iaddend. .Iadd.29. A one-chip monolithic semiconductor integrated circuit according to claim 27, wherein said digital signal storage means is a register; and   further including input buffer means between said external terminals and said digital signal storage means..Iaddend. .Iadd.30. A one-chip monolithic semiconductor integrated circuit according to claim 27, further including a digital signal output circuit having second input lines coupled to at least some of said data lines of said internal data bus for carrying digital output signals and having second output lines;   said digital signal output circuit having output buffers between said second output lines and said external terminals in common with said digital signal first input lines for buffering digital output signals; and   said output buffers being selectively activated for passing the digital output signals to said external terminals and being selectively deactivated for isolating said second output lines from said external terminals..Iaddend. .Iadd.31. A one-chip monolithic semiconductor integrated circuit according to claim 30, wherein said digital signal output circuit has digital signal output storage means coupled to said second input lines for storing digital output signals received from said internal data bus; and   wherein said digital signal output circuit further includes switches between said internal data bus and said digital signal output storage means..Iaddend. .Iadd.32. A one-chip monolithic semiconductor integrated circuit according to claim 31, wherein said second output lines of said digital signal output circuit are equal in number to and in pairs with respective ones of said digital signal first input lines, with each pair of digital signal first input line and second output line being coupled to   
     
     
        the same external terminal..Iaddend. .Iadd.33.  A one-chip monolithic semiconductor integrated circuit according to claim 30, wherein said second input lines of said digital signal output circuit are equal in number to and in pairs with respective ones of said first output lines of said digital signal input circuit, with each pair of first output lines of said digital signal input circuit and second input lines of said digital signal output circuit being coupled to the same data line of said internal data bus..Iaddend. .Iadd.34. A one-chip monolithic semiconductor integrated circuit according to claim 33, wherein said second output lines of said digital signal output circuit are equal in number to and in pairs with respective ones of said digital signal first input lines, with each pair of digital signal first input line and second output line being coupled to the same external terminal..Iaddend. .Iadd.35. A one-chip monolithic semiconductor integrated circuit according to claim 34, wherein said digital signal output circuit has digital signal output storage means coupled to said second input lines for storing digital output signals received from said internal data bus; and wherein said digital signal output circuit further includes switches between said internal data bus and said digital signal output storage means..Iaddend. .Iadd.36. A one-chip monolithic semiconductor integrated circuit according to claim 30, wherein said second output lines of said digital signal output circuit are equal in number to and in pairs with respective ones of said digital signal first input lines, with each pair of digital signal first input line and second output line being coupled to the same external terminal..Iaddend. .Iadd.37. A one-chip monolithic semiconductor integrated circuit according to claim 30, wherein said digital signal storage means is a register; and   further including input buffer means between said external terminals and said digital signal storage means..Iaddend. .Iadd.38. A one-chip monolithic semiconductor integrated circuit according to claim 27, wherein said analog signal input circuit includes a multiplexer having a plurality of input multiplexer lines respectively connected to said plurality of external terminals in common with said digital signal first input lines, having at least one multiplexer output line, and having at least one multiplexer select line for receiving a select signal to select only one of said input multiplexer lines to be directly connected to said multiplexer output line; and   an analog to digital converter having an input connected to said multiplexer output line and further having a plurality of digital outputs..Iaddend. .Iadd.39. A one-chip monolithic semiconductor integrated circuit according to claim 38, wherein said multiplexer has a plurality of multiplexer select lines and only one multiplexer output line; and   a decoder having a plurality of output lines respectively connected to said multiplexer select lines and a plurality of encoded signal input lines..Iaddend. .Iadd.40. A one-chip monolithic semiconductor integrated circuit according to claim 39, further including a latching circuit coupled to said encoded signal input lines, decoder switches between said latching circuit and said internal data bus, and said decoder switches having a switch activating line directly connected to said address decoder means..Iaddend. .Iadd.41. A one-chip monolithic semiconductor integrated circuit according to claim 40, wherein said address decoder means produces second selecting signals, said switch activating line of said decoder switches is directly connected to said address decoder means to receive the second selecting signals..Iaddend. .Iadd.42. A one-chip monolithic semiconductor integrated circuit according to claim 41, further including a storage directly connected to receive as inputs the digital outputs of said analog to digital converter;   a plurality of switches respectively connected between outputs of said storage and said data lines, and each having at least one activating, deactivating line connected to said address decoder means..Iaddend. .Iadd.43. A one-chip monolithic semiconductor integrated circuit according to claim 42, further including a digital signal output circuit having second input lines coupled to at least some of said data lines of said internal data bus for carrying digital output signals and having output lines;   said digital signal output circuit having output buffers between said second output lines and said external terminals in common with said digital signal first input lines for buffering digital output signals; and   said output buffers being selectively activated for passing the digital output signals to said external terminals and being selectively deactivated for isolating said second output lines from said external   
     
     
        terminals..Iaddend. .Iadd.44.  A one-chip monolithic semiconductor integrated circuit according to claim 43, wherein said digital signal output circuit has digital signal output storage means coupled to said second input lines for storing digital output signals received from said internal data bus; and wherein said digital signal output circuit further includes switches between said internal data bus and said digital signal output storage means..Iaddend. .Iadd.45. A one-chip monolithic semiconductor integrated circuit according to claim 44, wherein said second output lines of said digital signal output circuit are equal in number to and in pairs with respective ones of said digital signal first input lines, with each pair of digital signal first input line and second output line being coupled to the same external terminal..Iaddend. .Iadd.46. A one-chip monolithic semiconductor integrated circuit including a microprocessor, RAM and ROM, an internal data bus having data lines, an arithmetic and logic unit, and a plurality of external terminals, said microprocessor further comprising:   a digital signal input circuit having a plurality of digital signal input lines respectively coupled to said plurality of external terminals and having output lines;   an analog signal input circuit having an analog signal input line coupled to one of said plurality of external terminals in common with one of said digital signal input lines;   said output lines of said digital signal input circuit being respectively coupled to at least some of the data lines of said internal data bus;   a digital signal output circuit having digital signal output lines respectively coupled to said external terminals in common with said digital signal input lines and having input lines coupled to at least some of said data lines of said internal data bus for carrying digital output signals;   said digital signal output circuit including output buffer means for buffering the digital output signals;   said output buffer means being selectively activated for passing digital output signals to said external terminals and being selectively deactivated for isolating the digital output signals from said external terminals; and   address decoder means for receiving and decoding address signals to provide activating and deactivating digital signals to control activating and   
     
     
        deactivating of said output buffer means..Iaddend. .Iadd.47.  A one-chip monolithic semiconductor integrated circuit according to claim 46, wherein said digital signal output circuit further includes digital signal output storage means for storing the digital output signals received from said internal data bus, and output switches between said internal data bus and said digital signal output storage means; and wherein said digital signal output lines are equal in number to and in pairs with respective ones of said digital signal input lines, with each pair of digital signal input line and digital signal output line being coupled to the same external terminal..Iaddend. .Iadd.48. A one-chip monolithic semiconductor integrated circuit including a microprocessor, which includes an internal data bus having data lines, an arithmetic and logic unit, and a plurality of external terminals, said microprocessor further comprising:   a digital signal input circuit having a plurality of digital signal input lines respectively coupled to said plurality of external terminals and having output lines;   an analog signal input circuit having analog signal input lines coupled to said plurality of external terminals in common with one of said digital signal input lines of said digital signal input circuit;   said output lines of said digital signal input circuit being respectively coupled to at least some of the data lines of said internal data bus;   said analog input circuit including a multiplexer having a plurality of input multiplexer lines respectively connected to said plurality of external terminals in common with said digital signal input lines, having at least one multiplexer output line, and having multiplexer select lines for receiving select signals to select only one of said input multiplexer lines to be directly connected to said one multiplexer output line;   said analog input circuit further including an analog to digital converter having an input connected to said multiplexer output line and further having a plurality of digital outputs;   a decoder having a plurality of output lines respectively connected to said multiplexer select lines and a plurality of encoded signal input lines;   a latch circuit coupled to said encoded signal input lines;   a decoder switch between said latch circuit and said internal data bus, and having a switch activating line;   address decoder means for decoding address signals and producing a decoded output; and   said switch activating line of said decoder switch being directly connected to said address decoder means to receive the decoded output..Iaddend.   
     
     
        .Iadd.49.  A one-chip monolithic semiconductor integrated circuit according to claim 48, further including a storage directly connected to receive as inputs the digital outputs of said analog to digital converter..Iaddend. .Iadd.50. A one-chip monolithic semiconductor integrated circuit according to claim 48, including a plurality of switches respectively connected between said plurality of digital outputs of said analog to digital converter and different ones of said data lines, and each having at least one activating, deactivating line connected to said address decoder means..Iaddend. .Iadd.51. A one-chip monolithic semiconductor integrated circuit including a microprocessor, which includes an internal data bus having data lines, an arithmetic and logic unit, and a plurality of external terminals, said microprocessor further comprising: a digital signal input circuit having a plurality of digital signal input lines respectively coupled to said plurality of external terminals, and having output lines;   an analog signal input circuit having analog signal input lines coupled to said plurality of external terminals in common with said digital signal input lines;   said output lines of said digital signal input circuit being respectively coupled to at least some of the data lines of said internal data bus;   said analog input circuit including a multiplexer having a plurality of input multiplexer lines respectively connected to said plurality of external terminals in common with said digital signal input lines, having at least one multiplexer output line, and having multiplexer select lines for receiving select signals to select only one of said input multiplexer lines to be directly connected to said multiplexer output line;   said analog input circuit further including an analog to digital converter having an input connected to said multiplexer output line and further having a plurality of digital outputs;   a plurality of switches respectively connected between said plurality of digital outputs of said analog to digital converter and different ones of said data lines, and each having at least one activating, deactivating line;   address decoder means for decoding address signals and producing a decoded output; and   said activating, deactivating lines of said switches being directly connected to said address decoder means to receive the decoded output..Iaddend. .Iadd.52. A one-chip monolithic semiconductor integrated circuit according to claim 51, further including a digital signal output circuit having output lines and having input lines coupled to at least some of said data lines of said internal data bus for carrying digital output signals;   output buffer means between said external terminals in common with said digital signal input lines and said output lines of said digital signal output circuit for buffering digital output signals;   said output buffer means being selectively activated for passing digital output signals to said external terminals and being selectively deactivated for isolating digital output signals from said external terminals;   a decoder having a plurality of output lines respectively connected to said multiplexer select lines and a plurality of encoded signal input lines;   a latching circuit coupled to said encoded signal input lines;   a decoder switch between said latching circuit and said internal data bus having a switch activating line; and   said switch activating line of said decoder switch being directly connected to said address decoder means to receive the decoded output..Iaddend.