Schottky enhanced CMOS output circuit

Abstract

The high impedance state of a tri-state CMOS transistor output circuit is enhanced by serially connecting first and second Schottky diodes with the P-channel transistor and the N-channel transistor whereby in the high impedance state reverse bias of the substrate/source-drain diodes of the two transistors is prevented when the output of the circuit is taken beyond the supply voltage potentials of the output circuit.

What is claimed is: 
     
       1. A CMOS output circuit comprising: first and second voltage potentials;   a P-channel transistor having source, drain, and gate electrodes and an N-channel transistor having source, drain, and gate electrodes;   first input terminal means for applying a first input signal to said gate of said P-channel transistor;   second input terminal means for applying a second input signal to said gate electrode of said N-channel transistor;   a first Schottky diode connecting said source electrode of said P-channel transistor to said first voltage potential;   means connecting said source electrode of said N-channel transistor to said second voltage potential;   an output terminal connected to said drain electrode of said P-channel transistor; and   a second Schottky diode connecting said output terminal to said drain electrode of said N-channel transistor.   
     
     
       2. The CMOS output circuit as defined by claim 1 wherein said first voltage potential is more positive than said second voltage potential, said first Schottky diode being forward biased for current flow from said first voltage potential to said source electrode of said P-channel transistor, and said second Schottky diode being forward biased between said output terminal and said drain electrode of said N-channel transistor. 
     
     
       3. The CMOS output circuit as defined by claim 2 wherein said transistors are fabricated in a P-conductivity silicon substrate, said first and second Schottky diodes comprising N-doped wells in a surface of said substrate with respective metal contacts on the surfaces of the N-wells. 
     
     
       4. The CMOS output circuit of claim 3 wherein said first and second Schottky diodes further include respective N+ regions to facilitate contact with said respective metal contacts. 
     
     
       5. A CMOS output circuit comprising: first and second voltage potentials;   a P-channel transistor;   an N-channel transistor;   first input terminal means for applying a first input signal to a gate electrode of said P-channel transistor;   second input terminal means for applying a second input signal to a gate electrode of said N-channel transistor;   a first Schottky diode serially connected with said P-channel transistor between said first voltage potential and an output terminal; and   a second Schottky diode serially connected with said N-channel transistor between said output terminal and said second voltage potential. .Iadd.   
     
     
       6.  In an output circuit having an output terminal and first and second transistors which respectively couple first and second voltage potentials to said output terminal responsive to input signals applied to control electrodes of said first and second transistors, wherein at least one of said first and second transistors is an MOS transistor, an improvement comprising: a Schottky diode in series with said MOS transistor between said output terminal and one of said first and second voltage potentials. .Iaddend..Iadd.7. The output circuit of claim 6, wherein said MOS transistor is a P-channel transistor. .Iaddend..Iadd.8. The output circuit of claim 7, wherein said first voltage potential is more positive than said second voltage potential, said Schottky diode being forward biased for current flow from said first voltage potential to a source electrode of said P-channel transistor. .Iaddend..Iadd.9. The output circuit of claim 8, wherein said Schottky diode connects said source electrode of said P-channel transistor to said first voltage potential, and a drain electrode of said P-channel transistor is connected to said output terminal. .Iaddend..Iadd.10. The output circuit of claim 6, wherein said MOS transistor is an N-channel transistor. .Iaddend..Iadd.11. The output circuit of claim 10, wherein said first voltage potential is more positive than said second voltage potential, said Schottky diode being forward biased for current flow from said output terminal to a drain electrode of   
     
     
        said N-channel transistor. .Iaddend..Iadd.12.  The output circuit of claim 11, wherein said Schottky diode connects said drain electrode of said N-channel transistor to said output terminal, and a source electrode of said N-channel transistor is connected to said second voltage potential. .Iaddend..Iadd.13. The output circuit as defined by claims 6, 7, 8, 9, 10, 11 or 12 wherein said Schottky diode comprises an N-doped well in a surface of a P-conductivity silicon substrate, with a metal contact on the surface of said N-well. .Iaddend..Iadd.14. The output circuit of claim 13 wherein said Schottky diode further includes an N+ region to facilitate contact with said metal contact. .Iaddend.