Differential input amplifier stage with frequency compensation

Abstract

A differential input amplifier stage having improved frequency compensation. Frequency compensation is achieved by cancelling one-half of the signal output of a differential error amplifier in the input stage, such that all error signals must pass through a "current-mirror" type load circuit in which a resistor-capacitor network is provided to roll of gain of the input stage.

I claim: 
     
       1. An improved differential input amplifier stage having first and second input terminals between which a voltage difference can be generated, the stage including: an error amplifier circuit having a differential transistor pair coupled to the first and second input terminals for generating first and second differential currents responsive to a voltage difference generated between the first and second input terminals, at least a portion of each of the first and second differential currents being respectively coupled to first and second output terminals of the error amplifier circuit;   an active load coupled to the first and second output terminals of the error amplifier for generating an error signal current at an output terminal of the input stage by subtracting from the current generated at the second error amplifier output terminal a current conducted by the active load in response to the current generated at the first error amplifier output terminal; and   a frequency compensation circuit coupled to the active load to reduce the gain of the active load with respect to a range of frequencies, as a result of which the output voltage of the active load becomes less responsive to the current generated at the first error amplifier terminal at frequencies within the range of reduced gain;   wherein the improvement comprises:   means for dividing the first and second differential currents generated by the differential transistor pair into portions;   means for providing a first portion of the first differential current to the first output terminal of the error amplifier; and   means for combining a second portion of the first differential current with a portion of the second differential current to generate a current at the second output terminal of the error amplifier, whereby differential signals in the current generated at the second error amplifier output terminal are substantially cancelled.   
     
     
       2. The improved stage of claim 1, wherein the frequency compensation circuit comprises a network of resistor and capacitor elements, and wherein gain of the stage for signal frequencies within a predetermined range can be reduced below 0.5, the predetermined range being controllable by selectably varying values of the resistor and capacitor elements. 
     
     
       3. The improved stage of claim 1, wherein the currents generated at the first and second error amplifier output terminals are substantially equal when no voltage difference is generated between the first and second input terminals. 
     
     
       4. The improved stage of claim 1, wherein the differential transistor pair of the error amplifier circuit includes first and second transistors each having a first collector and a second collector, the first collector of the first transistor being coupled to the first output terminal of the error amplifier means, the second collector of each of the first and second transistors being commonly coupled to the second output terminal of the error amplifier circuit, and the first collector of the second transistor being coupled to a shunt point in the stage. 
     
     
       5. The improved stage of claim 4, wherein the second collectors of the first and second transistors are of substantially equal area. 
     
     
       6. The imnproved stage of claim 5, wherein the first and second collectors of each of the first and second transistors have a 2:1 area ratio. 
     
     
       7. The improved stage of claim 1, wherein the active load means comprises a current mirror circuit. 
     
     
       8. The improved stage of claim 1, wherein the stage is incorporated in an integrated circuit. 
     
     
       9. The improved stage of claim 1, wherein the stage is incorporated in a voltage regulator circuit. 
     
     
       10. A differential input amplifier stage having first and second input terminals between which a voltage difference can be generated, the stage including: a differential error amplifier circuit for generating first and second differential currents responsive to a voltage difference generated between the first and second input terminals, said second differential current being shunted;   a current source for providing a current substantially equal to a non-signal component of the first differential current;   an active load coupled to receive the first differential current and the current provided by the current source for generating an error signal current by subtracting from the current provided by the current source a current conducted by the active load in response to the first differential current; and   a frequency compensation circuit coupled to the active load to reduce the gain of the active load with respect to a range of high frequencies, as a result of which the output voltage of the active load becomes less responsive to the first differential current at frequencies within the range of reduced gain.   
     
     
       11. In a negative voltage regulator circuit having a common-emitter output stage including an output coupled to an output of the regulator and an input, and having voltage reference circuitry for generating a reference voltage, an input amplifier stage comprising: a differential error amplifier circuit having a first input coupled to receive the reference voltage and a second input coupled to receive a feedback signal responsive to the output of the regulator, said differential error amplifier operating to compare the reference voltage to a portion of the feedback signal to generate first and second differential currents;   an active load coupled to receive the first differential current and a second current substantially equal to a non-signal component of the first differential current for generating an error signal by subtracting the first differential current from the second current, at least a portion of the error signal being coupled to the input of the common-emitter output stage to control the output of the voltage regulator; and   a frequency compensation circuit coupled to the active load to reduce the gain of the active load with respect to a range of frequencies, as a result of which the output voltage of the active load becomes less responsive to the current generated by the error amplifier circuit at frequencies within the range of reduced gain.