Amplification circuit with a determined input impedance and various transconductance values

Abstract

A voltage-current amplification circuit comprises two sub-circuits (B1, B2), each of which comprises a differential amplifier (D), a resistor (R4), a transistor (T), and a first switch (K1) connected between the transistor base and ground. Each sub-circuit (B1, B2) also comprises an additional amplifier (A1, A2), and an additional resistor (R2a, R2b), respectively. The inputs of the additional amplifiers being connected to ground through a common resistor (R) and to the emitters of the two transistors through a common resistor (R1). Each sub-circuit further comprises a second switch (K2) formed by a single transistor.

We claim: 
     
       1. A voltage-current amplification circuit connected between an input terminal and first or second output terminals, said circuit comprising first and second sub-circuits, each sub-circuit comprising: (a) a first differential amplifier, a first input of which is connected to the input terminal through a first resistor,   (b) a transistor, .[.the.]. having a base connected to the output of the differential amplifier and having an emitter and a collector, and,   (c) a first switch connected between the transistor base and ground, the first sub-circuit comprising a second amplifier, the output of which is connected to a second input of the differential amplifier, and a second resistor connected between the transistor emitter and the first input of the differential amplifier,   the second sub-circuit comprising a third amplifier, the output of which is connected to the second input of the differential amplifier, and a third resistor connected between the transistor emitter and the first input of the differential amplifier,   the transistor collectors of the first and second sub-circuits being connected to the first and second output terminals, respectively, and the inputs of the second and third amplifiers being connected to ground through a common fourth resistor and to the emitters of the two transistors through a common fifth resistor,   wherein each said first and second sub-circuits further comprises a second switch connected between the first input of the differential amplifier and ground, each of said second switches being formed by a single transistor.     
     
     
       2. An amplification circuit according to claim 1, wherein each said first and second output terminals is connected to a different VTR head adapted respectively to a "normal duration" or "long duration" mode. 
     
     
       3. An amplication circuit according to claim 1, wherein gains of the second and third amplifiers are equal to R4/(R2a+R4) and R4/(R2b+R4), respectively, where R4 is the resistance value of the first resistor, R2a is the resistance value of the second resistor and R2b is the resistance value of the third resistor. 
     
     
       4. An amplification circuit according to claim 1, wherein each first switch is formed by a single transistor set to saturation mode when switched on. .Iadd. 
     
     
       5.  An amplification circuit, connected between an input terminal and first or second output terminals, comprising: first and second sub-circuits each including: (a) a first differential amplifier, a first input of which is connected to the said input terminal through a first resistor,   (b) a transistor having a control terminal thereof connected to an output of said differential amplifier, and having first and second current-carrying terminals; and   (c) a first switch connected between said control terminal and a reference potential;     said first sub-circuit further comprising a second amplifier, having an output thereof connected to a second input of said respective differential amplifier, and a second resistor connected between said first current-carrying terminal and said first input of said respective differential amplifier,   said second sub-circuit further comprising a third amplifier having an output thereof connected to a second input of said respective differential amplifier, and a third resistor connected between said first current-carrying terminal and said first input of said respective differential amplifier,   said second current-carrying terminals of said respective transistors of the first and second sub-circuits being connected to said first and second output terminals, respectively, and said inputs of the second and third amplifiers being connected to said reference potential through a common fourth resistor and to said respective first current-carrying terminals through a common fifth resistor,   wherein each of said first and second sub-circuits further comprises a second switch connected between the first input of the differential amplifier and said reference potential, each of said second switches being formed by a single transistor. .Iaddend..Iadd.   
     
     
       6.  The circuit of claim 5, wherein said transistor is bipolar, and said first and second current-carrying terminals thereof correspond to an emitter thereof and a collector thereof respectively. .Iaddend..Iadd.7. The circuit of claim 5, wherein each said first and second output terminals is connected to a different VTR head adapted respectively to a "normal duration" or "long duration" mode. .Iaddend..Iadd.8. The circuit of claim 5, wherein gains of said second and third amplifiers are equal to R4/(R2a+R4) and R4/(R2b+R4), respectively, where R4 is the resistance value of the first resistor, R2a is the resistance value of the second resistor and R2b is the resistance value of the third resistor. .Iaddend..Iadd.9. The circuit of claim 5, wherein each first switch is formed by a single transistor connected and configured to operate in 
     
     
        saturation mode when switched on. .Iaddend..Iadd.10.  An amplification circuit, connected between an input terminal and first or second output terminals, comprising: first and second sub-circuits each including: (a) a first differential amplifier, a first input of which is connected to said input terminal through a first resistor,   (b) a transistor having a base connected to the output of the differential amplifier and having an emitter and a collector, and,   (c) a first switch connected between said base and a reference potential;     said first sub-circuit further comprising a second amplifier, having an output thereof connected to a second input of said respective differential amplifier, and a second resistor connected between said emitter and said first input of said respective differential amplifier,   said second sub-circuit further comprising a third amplifier having an output thereof connected to a second input of said respective differential amplifier, and a third resistor connected between said emitter and said first input of said respective differential amplifier,   said collectors of said respective transistors of the first and second sub-circuits being connected to said first and second output terminals, respectively, and said inputs of the second and third amplifiers being connected to said reference potential through a common fourth resistor and to said respective emitter through a common fifth resistor,   wherein each of said first and second sub-circuits further comprises a second switch connected between the first input of the differential amplifier and said reference potential. .Iaddend..Iadd.11. The circuit of claim 10, wherein each said first and second output terminals is connected to a different VTR head adapted respectively to a "normal duration" or   
     
     
        "long duration" mode. .Iaddend..Iadd.12.  The circuit of claim 10, wherein said second switch consists of a single transistor. .Iaddend..Iadd.13. The circuit of claim 10, wherein gains of said second and third amplifiers are equal to R4/(R2a+R4) and R4/(R2b+R4), respectively, where R4 is the resistance value of the first resistor, R2a is the resistance value of the second resistor and R2b is the resistance value of the third resistor. .Iaddend..Iadd.14. The circuit of claim 10, wherein each first switch is formed by a single transistor connected and configured to operate in 
     
     
        saturation mode when switched on. .Iaddend..Iadd.15.  An amplification circuit, connected between an input terminal and first or second output terminals, comprising: first and second sub-circuits each including: (a) a first differential amplifier, a first input of which is connected to said input terminal through a first resistor,   (b) a transistor having a control terminal thereof connected to an output of said differential amplifier, and having first and second current-carrying terminals; and   (c) a first switch connected between said control terminal and a reference potential;     said first sub-circuit further comprising a second amplifier, having an output thereof connected to a second input of said respective differential amplifier, and a second resistor connected between said first current-carrying terminal and said first input of said respective differential amplifier,   said second sub-circuit further comprising a third amplifier having an output thereof connected to a second input of said respective differential amplifier, and a third resistor connected between said first current-carrying terminal and said first input of said respective differential amplifier,   said second current-carrying terminals of said respective transistors of the first and second sub-circuits being connected to said first and second output terminals, respectively, and said inputs of the second and third amplifiers being jointly connected to said reference potential through a fourth resistor and to said respective first current-carrying terminals through a fifth resistor,   wherein each of said first and second sub-circuits further comprises a second switch connected between the first input of the differential   
     
     
        amplifier and said reference potential. .Iaddend..Iadd.16.  The circuit of claim 15, wherein said transistor is bipolar, and said first and second current-carrying terminals thereof correspond to an emitter thereof and a collector thereof respectively. .Iaddend..Iadd.17. The circuit of claim 15, wherein each said first and second output terminals is connected to a different VTR head adapted respectively to a "normal duration" or "long duration" mode. .Iaddend..Iadd.18. The circuit of claim 15, wherein said transistor is bipolar, and said first and second current-carrying terminals thereof correspond to an emitter thereof and a collector thereof respectively, and wherein said second switch consists of a single transistor. .Iaddend..Iadd.19. The circuit of claim 15, wherein gains of said second and third amplifiers are equal to R4/(R2a+R4) and R4/(R2b+R4), respectively, where R4 is the resistance value of the first resistor, R2a is the resistance value of the second resistor and R2b is the resistance value of the third resistor. .Iaddend..Iadd.20. The circuit of claim 15, wherein each first switch is formed by a single transistor connected and configured to operate in saturation mode when switched on. .Iaddend.