Method of manufacturing semiconductor device utilizing an accumulation layer

Abstract

A method of manufacturing semiconductor devices by forming a U-shaped insulated gate on a substrate, etching the substrate to expose a sidewall of the U-shaped insulated gate, covering the exposed part with a masking material, forming the sidewall of the masking material only adjoining to the exposed U-shaped insulated gate, etching the substrate vertically to form a groove, forming a semiconductor region on the groove and burying a metal into the groove.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming at least one U-shaped insulated gate on a surface of a first conductivity type semiconductor substrate;   (b) exposing part of a sidewall of said U-shaped insulated gate by etching said substrate;   (c) covering the exposed part with a masking material;   (d) forming the sidewall of said masking material only adjoining to a side of said exposed part of said U-shaped insulated gate;   (e) forming at least one groove by etching said substrate almost vertically using said masking material sidewall as a mask; and   (f) forming a second conductivity type semiconductor region on a surface of said groove and burying metal into said groove.   
     
     
       2. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming at least one U-shaped insulated gate on a surface of a first conductivity type semiconductor substrate;   (b) exposing part of a sidewall of said U-shaped insulated gate by etching said substrate;   (c) covering the exposed part with a masking material;   (d) forming the sidewall of said masking material only adjoining to a side of said exposed part of said U-shaped insulated gate;   (e) forming at least one groove by etching said substrate almost vertically using said masking material sidewall as a mask; and   (f) burying metal into said groove and forming a Schottky junction with said substrate.   
     
     
       3. A method of manufacturing a semiconductor device, comprising the steps of: (a) forming at least one U-shaped insulated gate on a surface of a first conductivity type semiconductor substrate;   (b) exposing part of a sidewall of said U-shaped insulated gate by etching said substrate;   (c) covering the exposed part with a masking material;   (d) forming the sidewall of said masking material only adjoining to a side of said exposed part of said U-shaped insulated gate;   (e) forming at least one groove by etching said substrate almost vertically using said masking material sidewall as a mask; and   (f) forming another insulated gate on a surface of said groove and burying metal into said groove.   
     
     
       4. The method of claim 1, wherein said masking material is an insulator containing first conductivity type impurity atoms at high concentration, and which further comprises the step of forming a source region under the sidewall by annealing to diffuse impurity atoms from said masking material to said substrate region adjoining to said masking material after the sidewall has been formed. 
     
     
       5. The method of claim 1, wherein said masking material is a polycrystalline semiconductor containing first conductivity type impurity atoms at high concentration, and which further comprises the step of forming a source region under the sidewall by annealing to diffuse impurity atoms from said masking material to said substrate region adjoining to said masking material after the sidewall has been formed. 
     
     
       6. The method of claim 1, wherein said masking material is an amorphous semiconductor containing first conductivity type impurity atoms at high concentration, and which further comprises the step of forming a source region under the sidewall by annealing to diffuse impurity atoms from said masking material to said substrate region adjoining to said masking material after the sidewall has been formed. 
     
     
       7. A method of manufacturing a semiconductor device, which has a first conductivity type source region on a surface of a first conductivity type semiconductor substrate and has a .Iadd.semiconductor .Iaddend.region put between an insulated gate and a metal forming .Iadd.a .Iaddend.Schottky junction with said substrate and having the same electrical potential as said source region, .Iadd.said semiconductor region being a part of said semiconductor substrate, .Iaddend.comprising the steps of: (a) forming a first conductivity type and high impurity concentration source region on the surface of the first conductivity type semiconductor substrate;   (b) forming masking films on said source region;   (c) removing part of said films for a gate electrode;   (d) shallowly removing a part of the source region by .[.anisotropic.]. .Iadd.isotropic .Iaddend.etching to form a side-etched portion under said masking films;   (e) deeply removing said substrate by .[.isotropic.]. .Iadd.anisotropic .Iaddend.etching using said masking films as a mask to form a groove for a gate electrode;   (f) forming a gate oxide film on a surface of said gate groove;   (g) burying a conductive material into said groove as the gate electrode;   (h) forming an interlayer insulating film on a surface of said gate material to form a T-shaped cross-sectional insulated gate electrode;   (i) removing the remaining masking films on a surface of said source region;   (j) deeply removing said substrate by .[.isotropic.]. .Iadd.anisotropic .Iaddend.etching by using said T-shaped insulated gate as a mask to form almost a vertical groove; and   (k) burying metal into said groove as a source electrode.